_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity c_dds_v3_1 is
    generic(
        c_accumulator_latency: integer := 1;
        c_accumulator_width: integer := 16;
        c_data_width    : integer := 16;
        c_enable_rlocs  : integer := 0;
        c_has_aclr      : integer := 0;
        c_has_ce        : integer := 0;
        c_has_rdy       : integer := 1;
        c_has_rfd       : integer := 0;
        c_has_sclr      : integer := 0;
        c_latency       : integer := 0;
        c_mem_type      : integer := 0;
        c_negative_cosine: integer := 0;
        c_negative_sine : integer := 0;
        c_noise_shaping : integer := 0;
        c_outputs_required: integer := 2;
        c_output_width  : integer := 16;
        c_phase_angle_width: integer := 4;
        c_phase_increment: integer := 1;
        c_phase_increment_value: string  := "0";
        c_phase_offset  : integer := 2;
        c_phase_offset_value: string  := "0";
        c_pipelined     : integer := 1
    );
    port(
        a               : in     vl_logic;
        aclr            : in     vl_logic;
        ce              : in     vl_logic;
        clk             : in     vl_logic;
        cosine          : out    vl_logic_vector;
        data            : in     vl_logic_vector;
        rdy             : out    vl_logic;
        rfd             : out    vl_logic;
        sclr            : in     vl_logic;
        sine            : out    vl_logic_vector;
        we              : in     vl_logic
    );
end c_dds_v3_1;