_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity dither_v4_0 is
    generic(
        hasainit        : integer := 0;
        hasce           : integer := 0;
        hassinit        : integer := 0;
        lfsralength     : integer := 13;
        lfsrblength     : integer := 14;
        lfsrclength     : integer := 15;
        lfsrdlength     : integer := 16;
        pipelined       : integer := 1
    );
    port(
        ainit           : in     vl_logic;
        ce              : in     vl_logic;
        clk             : in     vl_logic;
        dither          : out    vl_logic;
        sinit           : in     vl_logic
    );
end dither_v4_0;