_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity sid_v1_1 is
    generic(
        c_add_symmetry_constraint: integer := 0;
        c_block_size_constant: integer := 256;
        c_block_size_type: integer := 0;
        c_block_size_width: integer := 8;
        c_branch_length_constant: integer := 1;
        c_branch_length_file: string  := "null.mif";
        c_branch_length_type: integer := 0;
        c_col_constant  : integer := 16;
        c_col_permute_file: string  := "null.mif";
        c_col_select_file: string  := "null.mif";
        c_col_type      : integer := 0;
        c_col_width     : integer := 4;
        c_enable_rlocs  : integer := 1;
        c_family_int    : integer := 0;
        c_has_aclr      : integer := 0;
        c_has_block_end : integer := 0;
        c_has_block_size: integer := 0;
        c_has_block_size_valid: integer := 0;
        c_has_block_start: integer := 0;
        c_has_ce        : integer := 0;
        c_has_col       : integer := 0;
        c_has_col_sel   : integer := 0;
        c_has_col_sel_valid: integer := 0;
        c_has_fdo       : integer := 0;
        c_has_ndo       : integer := 0;
        c_has_rdy       : integer := 0;
        c_has_rfd       : integer := 0;
        c_has_rffd      : integer := 0;
        c_has_row       : integer := 0;
        c_has_row_sel   : integer := 0;
        c_has_row_sel_valid: integer := 0;
        c_has_sclr      : integer := 0;
        c_k             : integer := 2;
        c_memstyle      : integer := 2;
        c_mem_init_prefix: string  := "sid1";
        c_mode          : integer := 0;
        c_n1            : integer := 3;
        c_n2            : integer := 1;
        c_num_branches  : integer := 16;
        c_num_selectable_cols: integer := 4;
        c_num_selectable_rows: integer := 4;
        c_pipe_level    : integer := 1;
        c_relative_prime: integer := 1;
        c_row_constant  : integer := 16;
        c_row_permute_file: string  := "null.mif";
        c_row_select_file: string  := "null.mif";
        c_row_type      : integer := 0;
        c_row_width     : integer := 4;
        c_seed          : integer := 0;
        c_spread1       : integer := 1;
        c_spread2       : integer := 1;
        c_symbol_width  : integer := 1;
        c_throughput_mode: integer := 0;
        c_type          : integer := 20;
        c_use_col_permute_file: integer := 0;
        c_use_k         : integer := 0;
        c_use_row_permute_file: integer := 0;
        c_use_spreads   : integer := 0
    );
    port(
        clk             : in     vl_logic;
        fd              : in     vl_logic;
        nd              : in     vl_logic;
        din             : in     vl_logic_vector;
        ce              : in     vl_logic;
        sclr            : in     vl_logic;
        aclr            : in     vl_logic;
        row             : in     vl_logic_vector;
        row_sel         : in     vl_logic_vector;
        col             : in     vl_logic_vector;
        col_sel         : in     vl_logic_vector;
        block_size      : in     vl_logic_vector;
        np              : in     vl_logic;
        p0              : in     vl_logic_vector(5 downto 0);
        p1              : in     vl_logic_vector(9 downto 0);
        p2              : in     vl_logic_vector(9 downto 0);
        p3              : in     vl_logic_vector(9 downto 0);
        dout            : out    vl_logic_vector;
        rfd             : out    vl_logic;
        rdy             : out    vl_logic;
        rffd            : out    vl_logic;
        row_sel_valid   : out    vl_logic;
        col_sel_valid   : out    vl_logic;
        block_size_valid: out    vl_logic;
        block_start     : out    vl_logic;
        block_end       : out    vl_logic;
        fdo             : out    vl_logic;
        ndo             : out    vl_logic
    );
end sid_v1_1;