_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity c_mux_bus_v5_0 is
    generic(
        c_ainit_val     : string  := "";
        c_enable_rlocs  : integer := 1;
        c_has_aclr      : integer := 0;
        c_has_ainit     : integer := 0;
        c_has_aset      : integer := 0;
        c_has_ce        : integer := 0;
        c_has_en        : integer := 0;
        c_has_o         : integer := 0;
        c_has_q         : integer := 1;
        c_has_sclr      : integer := 1;
        c_has_sinit     : integer := 0;
        c_has_sset      : integer := 1;
        c_inputs        : integer := 2;
        c_latency       : integer := 1;
        c_mux_type      : integer := 0;
        c_sel_width     : integer := 1;
        c_sinit_val     : string  := "";
        c_sync_enable   : integer := 0;
        c_sync_priority : integer := 1;
        c_width         : integer := 2
    );
    port(
        ma              : in     vl_logic_vector;
        mb              : in     vl_logic_vector;
        mc              : in     vl_logic_vector;
        md              : in     vl_logic_vector;
        me              : in     vl_logic_vector;
        mf              : in     vl_logic_vector;
        mg              : in     vl_logic_vector;
        mh              : in     vl_logic_vector;
        maa             : in     vl_logic_vector;
        mab             : in     vl_logic_vector;
        mac             : in     vl_logic_vector;
        mad             : in     vl_logic_vector;
        mae             : in     vl_logic_vector;
        maf             : in     vl_logic_vector;
        mag             : in     vl_logic_vector;
        mah             : in     vl_logic_vector;
        mba             : in     vl_logic_vector;
        mbb             : in     vl_logic_vector;
        mbc             : in     vl_logic_vector;
        mbd             : in     vl_logic_vector;
        mbe             : in     vl_logic_vector;
        mbf             : in     vl_logic_vector;
        mbg             : in     vl_logic_vector;
        mbh             : in     vl_logic_vector;
        mca             : in     vl_logic_vector;
        mcb             : in     vl_logic_vector;
        mcc             : in     vl_logic_vector;
        mcd             : in     vl_logic_vector;
        mce             : in     vl_logic_vector;
        mcf             : in     vl_logic_vector;
        mcg             : in     vl_logic_vector;
        mch             : in     vl_logic_vector;
        s               : in     vl_logic_vector;
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        en              : in     vl_logic;
        aclr            : in     vl_logic;
        aset            : in     vl_logic;
        ainit           : in     vl_logic;
        sclr            : in     vl_logic;
        sset            : in     vl_logic;
        sinit           : in     vl_logic;
        o               : out    vl_logic_vector;
        q               : out    vl_logic_vector
    );
end c_mux_bus_v5_0;