_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity c_counter_binary_v1_0 is
    generic(
        c_ainit_val     : string  := "0";
        c_count_by      : string  := "";
        c_count_mode    : integer := 0;
        c_count_to      : string  := "";
        c_enable_rlocs  : integer := 0;
        c_has_aclr      : integer := 0;
        c_has_ainit     : integer := 0;
        c_has_aset      : integer := 0;
        c_has_ce        : integer := 0;
        c_has_iv        : integer := 0;
        c_has_l         : integer := 0;
        c_has_load      : integer := 0;
        c_has_q_thresh0 : integer := 0;
        c_has_q_thresh1 : integer := 0;
        c_has_sclr      : integer := 0;
        c_has_sinit     : integer := 0;
        c_has_sset      : integer := 0;
        c_has_thresh0   : integer := 0;
        c_has_thresh1   : integer := 0;
        c_has_up        : integer := 0;
        c_load_enable   : integer := 0;
        c_load_low      : integer := 0;
        c_pipe_stages   : integer := 0;
        c_restrict_count: integer := 1;
        c_sinit_val     : string  := "0";
        c_sync_enable   : integer := 0;
        c_sync_priority : integer := 1;
        c_thresh0_value : string  := "";
        c_thresh1_value : string  := "";
        c_width         : integer := 16;
        c_out_type      : integer := 0
    );
    port(
        clk             : in     vl_logic;
        up              : in     vl_logic;
        ce              : in     vl_logic;
        load            : in     vl_logic;
        l               : in     vl_logic_vector;
        iv              : in     vl_logic_vector;
        aclr            : in     vl_logic;
        aset            : in     vl_logic;
        ainit           : in     vl_logic;
        sclr            : in     vl_logic;
        sset            : in     vl_logic;
        sinit           : in     vl_logic;
        thresh0         : out    vl_logic;
        q_thresh0       : out    vl_logic;
        thresh1         : out    vl_logic;
        q_thresh1       : out    vl_logic;
        q               : out    vl_logic_vector
    );
end c_counter_binary_v1_0;