_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity vfft32_input_working_result_memory_v2_0 is
    generic(
        result_width    : integer := 5;
        points_power    : integer := 5;
        b               : integer := 12;
        data_memory     : string  := "";
        zero_data       : integer := 0;
        one_string      : integer := 1;
        three           : integer := 3;
        ainit_val       : integer := 0;
        sinit_val       : integer := 0;
        ainit_val_ascii : integer := 48;
        sinit_val_ascii : integer := 48
    );
    port(
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        reset           : in     vl_logic;
        fwd_inv         : in     vl_logic;
        y0r             : in     vl_logic_vector;
        y0i             : in     vl_logic_vector;
        y1r             : in     vl_logic_vector;
        y1i             : in     vl_logic_vector;
        y2r             : in     vl_logic_vector;
        y2i             : in     vl_logic_vector;
        y3r             : in     vl_logic_vector;
        y3i             : in     vl_logic_vector;
        dia_r           : in     vl_logic_vector;
        dia_i           : in     vl_logic_vector;
        xn_re           : in     vl_logic_vector;
        xn_im           : in     vl_logic_vector;
        ena             : in     vl_logic;
        wea             : in     vl_logic;
        addra           : in     vl_logic_vector;
        addra_dmem      : in     vl_logic_vector;
        xn_r            : in     vl_logic_vector;
        xn_i            : in     vl_logic_vector;
        data_sel        : in     vl_logic_vector(1 downto 0);
        we_dmem         : in     vl_logic;
        web             : in     vl_logic;
        addrb           : in     vl_logic_vector;
        addrb_dmem      : in     vl_logic_vector;
        result_avail    : in     vl_logic;
        reading_result  : in     vl_logic;
        writing_result  : in     vl_logic;
        mem_outr        : out    vl_logic_vector;
        mem_outi        : out    vl_logic_vector;
        xk_result_out_re: out    vl_logic_vector;
        xk_result_out_im: out    vl_logic_vector
    );
end vfft32_input_working_result_memory_v2_0;