_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity ifddrcpe is
    port(
        q0              : out    vl_logic;
        q1              : out    vl_logic;
        c0              : in     vl_logic;
        c1              : in     vl_logic;
        ce              : in     vl_logic;
        clr             : in     vl_logic;
        d               : in     vl_logic;
        pre             : in     vl_logic
    );
end ifddrcpe;