untitled3.rpt

基于maxplusII的EDA设计

                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (40)    18    B       TFFE   +  t        0      0   0    0    2    8    0  |74161:1|p74161:sub|QC (|74161:1|p74161:sub|:7)
 (41)    17    B       TFFE   +  t        0      0   0    0    1    8    1  |74161:1|p74161:sub|QB (|74161:1|p74161:sub|:8)
 (33)    24    B       TFFE   +  t        0      0   0    0    0    8    2  |74161:1|p74161:sub|QA (|74161:1|p74161:sub|:9)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                    c:\max2work\vhdl\untitled3.rpt
untitled3

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                               Logic cells placed in LAB 'B'
        +--------------------- LC25 1
        | +------------------- LC27 2
        | | +----------------- LC26 3
        | | | +--------------- LC23 4
        | | | | +------------- LC22 5
        | | | | | +----------- LC21 6
        | | | | | | +--------- LC20 7
        | | | | | | | +------- LC19 8
        | | | | | | | | +----- LC18 |74161:1|p74161:sub|QC
        | | | | | | | | | +--- LC17 |74161:1|p74161:sub|QB
        | | | | | | | | | | +- LC24 |74161:1|p74161:sub|QA
        | | | | | | | | | | | 
        | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC18 -> * * * * * * * * * - - | - * | <-- |74161:1|p74161:sub|QC
LC17 -> * * * * * * * * * * - | - * | <-- |74161:1|p74161:sub|QB
LC24 -> * * * * * * * * * * * | - * | <-- |74161:1|p74161:sub|QA

Pin
43   -> - - - - - - - - - - - | - - | <-- PIN_NAME


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                    c:\max2work\vhdl\untitled3.rpt
untitled3

** EQUATIONS **

PIN_NAME : INPUT;

-- Node name is '1' 
-- Equation name is '1', location is LC025, type is output.
 1       = LCELL( _EQ001 $  GND);
  _EQ001 = !_LC017 & !_LC018 & !_LC024;

-- Node name is '2' 
-- Equation name is '2', location is LC027, type is output.
 2       = LCELL( _EQ002 $  GND);
  _EQ002 = !_LC017 & !_LC018 &  _LC024;

-- Node name is '3' 
-- Equation name is '3', location is LC026, type is output.
 3       = LCELL( _EQ003 $  GND);
  _EQ003 =  _LC017 & !_LC018 & !_LC024;

-- Node name is '4' 
-- Equation name is '4', location is LC023, type is output.
 4       = LCELL( _EQ004 $  GND);
  _EQ004 =  _LC017 & !_LC018 &  _LC024;

-- Node name is '5' 
-- Equation name is '5', location is LC022, type is output.
 5       = LCELL( _EQ005 $  GND);
  _EQ005 = !_LC017 &  _LC018 & !_LC024;

-- Node name is '6' 
-- Equation name is '6', location is LC021, type is output.
 6       = LCELL( _EQ006 $  GND);
  _EQ006 = !_LC017 &  _LC018 &  _LC024;

-- Node name is '7' 
-- Equation name is '7', location is LC020, type is output.
 7       = LCELL( _EQ007 $  GND);
  _EQ007 =  _LC017 &  _LC018 & !_LC024;

-- Node name is '8' 
-- Equation name is '8', location is LC019, type is output.
 8       = LCELL( _EQ008 $  GND);
  _EQ008 =  _LC017 &  _LC018 &  _LC024;

-- Node name is '|74161:1|p74161:sub|:9' = '|74161:1|p74161:sub|QA' 
-- Equation name is '_LC024', type is buried 
_LC024   = TFFE( VCC, GLOBAL( PIN_NAME),  VCC,  VCC,  VCC);

-- Node name is '|74161:1|p74161:sub|:8' = '|74161:1|p74161:sub|QB' 
-- Equation name is '_LC017', type is buried 
_LC017   = TFFE( _LC024, GLOBAL( PIN_NAME),  VCC,  VCC,  VCC);

-- Node name is '|74161:1|p74161:sub|:7' = '|74161:1|p74161:sub|QC' 
-- Equation name is '_LC018', type is buried 
_LC018   = TFFE( _EQ009, GLOBAL( PIN_NAME),  VCC,  VCC,  VCC);
  _EQ009 =  _LC017 &  _LC024;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                             c:\max2work\vhdl\untitled3.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,258K