kaiguan.vhd

来自「基于maxplusII的EDA设计」· VHDL 代码 · 共 18 行

library ieee;
use ieee.std_logic_1164.all;
entity kaiguan is
   port(a0,a1:in std_logic;
           b0:out std_logic);
end kaiguan;
architecture kaiguan_arc of kaiguan is
    begin
       process(a0,a1)
          begin
           if a1='1'then
              b0<=a0;
           else
              b0<='0';
           end if;
       end process;
    end kaiguan_arc;