📄 jsmk.rpt
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-- Node name is '1d5'
-- Equation name is '1d5', type is output
1d5 = _LC7_A35;
-- Node name is '1d6'
-- Equation name is '1d6', type is output
1d6 = _LC3_A19;
-- Node name is '1d7'
-- Equation name is '1d7', type is output
1d7 = _LC4_A19;
-- Node name is '2d0'
-- Equation name is '2d0', type is output
2d0 = _LC1_A19;
-- Node name is '2d1'
-- Equation name is '2d1', type is output
2d1 = _LC8_A19;
-- Node name is '2d2'
-- Equation name is '2d2', type is output
2d2 = _LC6_A19;
-- Node name is '2d3'
-- Equation name is '2d3', type is output
2d3 = _LC2_A19;
-- Node name is '|74161:1|f74161:sub|:9' = '|74161:1|f74161:sub|QA'
-- Equation name is '_LC5_A29', type is buried
_LC5_A29 = DFFE( _EQ001, GLOBAL( clk), GLOBAL( clrn), VCC, VCC);
_EQ001 = en & !_LC5_A29
# !en & !_LC1_A35 & _LC5_A29;
-- Node name is '|74161:1|f74161:sub|:87' = '|74161:1|f74161:sub|QB'
-- Equation name is '_LC2_A35', type is buried
_LC2_A35 = DFFE( _EQ002, GLOBAL( clk), GLOBAL( clrn), VCC, VCC);
_EQ002 = _LC2_A35 & _LC4_A35 & !_LC5_A29
# !en & _LC2_A35 & _LC4_A35
# en & !_LC2_A35 & _LC4_A35 & _LC5_A29;
-- Node name is '|74161:1|f74161:sub|:99' = '|74161:1|f74161:sub|QC'
-- Equation name is '_LC3_A35', type is buried
_LC3_A35 = DFFE( _EQ003, GLOBAL( clk), GLOBAL( clrn), VCC, VCC);
_EQ003 = _LC3_A35 & _LC4_A35 & !_LC6_A35
# !_LC3_A35 & _LC4_A35 & _LC6_A35;
-- Node name is '|74161:1|f74161:sub|:110' = '|74161:1|f74161:sub|QD'
-- Equation name is '_LC1_A35', type is buried
_LC1_A35 = DFFE( _EQ004, GLOBAL( clk), GLOBAL( clrn), VCC, VCC);
_EQ004 = _LC1_A35 & !_LC3_A35 & _LC4_A35
# _LC1_A35 & _LC4_A35 & !_LC6_A35
# !_LC1_A35 & _LC3_A35 & _LC4_A35 & _LC6_A35;
-- Node name is '|74161:1|f74161:sub|:96'
-- Equation name is '_LC6_A35', type is buried
_LC6_A35 = LCELL( _EQ005);
_EQ005 = en & _LC2_A35 & _LC5_A29;
-- Node name is '|74161:2|f74161:sub|:9' = '|74161:2|f74161:sub|QA'
-- Equation name is '_LC8_A35', type is buried
_LC8_A35 = DFFE( _EQ006, GLOBAL( clk), GLOBAL( clrn), VCC, VCC);
_EQ006 = _LC4_A35 & !_LC7_A19 & _LC8_A35
# !_LC4_A35 & !_LC7_A19 & !_LC8_A35;
-- Node name is '|74161:2|f74161:sub|:87' = '|74161:2|f74161:sub|QB'
-- Equation name is '_LC7_A35', type is buried
_LC7_A35 = DFFE( _EQ007, GLOBAL( clk), GLOBAL( clrn), VCC, VCC);
_EQ007 = !_LC7_A19 & _LC7_A35 & !_LC8_A35
# _LC4_A35 & !_LC7_A19 & _LC7_A35
# !_LC4_A35 & !_LC7_A19 & !_LC7_A35 & _LC8_A35;
-- Node name is '|74161:2|f74161:sub|:99' = '|74161:2|f74161:sub|QC'
-- Equation name is '_LC3_A19', type is buried
_LC3_A19 = DFFE( _EQ008, GLOBAL( clk), GLOBAL( clrn), VCC, VCC);
_EQ008 = _LC3_A19 & !_LC5_A35 & !_LC7_A19
# !_LC3_A19 & _LC5_A35 & !_LC7_A19;
-- Node name is '|74161:2|f74161:sub|:110' = '|74161:2|f74161:sub|QD'
-- Equation name is '_LC4_A19', type is buried
_LC4_A19 = DFFE( _EQ009, GLOBAL( clk), GLOBAL( clrn), VCC, VCC);
_EQ009 = !_LC3_A19 & _LC4_A19 & !_LC7_A19
# _LC4_A19 & !_LC5_A35 & !_LC7_A19
# _LC3_A19 & !_LC4_A19 & _LC5_A35 & !_LC7_A19;
-- Node name is '|74161:2|f74161:sub|:96'
-- Equation name is '_LC5_A35', type is buried
_LC5_A35 = LCELL( _EQ010);
_EQ010 = _LC1_A35 & _LC5_A29 & _LC7_A35 & _LC8_A35;
-- Node name is '|74161:14|f74161:sub|:9' = '|74161:14|f74161:sub|QA'
-- Equation name is '_LC2_A19', type is buried
_LC2_A19 = DFFE( _EQ011, GLOBAL( clk), GLOBAL( clrn), VCC, VCC);
_EQ011 = !_LC2_A19 & _LC7_A19
# !_LC1_A19 & _LC2_A19 & !_LC7_A19;
-- Node name is '|74161:14|f74161:sub|:87' = '|74161:14|f74161:sub|QB'
-- Equation name is '_LC6_A19', type is buried
_LC6_A19 = DFFE( _EQ012, GLOBAL( clk), GLOBAL( clrn), VCC, VCC);
_EQ012 = !_LC2_A19 & _LC6_A19
# !_LC1_A19 & _LC6_A19 & !_LC7_A19
# !_LC1_A19 & _LC2_A19 & !_LC6_A19 & _LC7_A19;
-- Node name is '|74161:14|f74161:sub|:99' = '|74161:14|f74161:sub|QC'
-- Equation name is '_LC8_A19', type is buried
_LC8_A19 = DFFE( _EQ013, GLOBAL( clk), GLOBAL( clrn), VCC, VCC);
_EQ013 = !_LC2_A19 & !_LC5_A19 & _LC8_A19
# !_LC1_A19 & !_LC5_A19 & _LC8_A19
# !_LC2_A19 & _LC5_A19 & !_LC8_A19
# !_LC1_A19 & _LC5_A19 & !_LC8_A19;
-- Node name is '|74161:14|f74161:sub|:110' = '|74161:14|f74161:sub|QD'
-- Equation name is '_LC1_A19', type is buried
_LC1_A19 = DFFE( _EQ014, GLOBAL( clk), GLOBAL( clrn), VCC, VCC);
_EQ014 = !_LC1_A19 & _LC5_A19 & _LC8_A19
# _LC1_A19 & !_LC2_A19 & !_LC8_A19
# _LC1_A19 & !_LC2_A19 & !_LC5_A19;
-- Node name is '|74161:14|f74161:sub|:96'
-- Equation name is '_LC5_A19', type is buried
_LC5_A19 = LCELL( _EQ015);
_EQ015 = _LC2_A19 & _LC6_A19 & _LC7_A19;
-- Node name is ':8'
-- Equation name is '_LC4_A35', type is buried
_LC4_A35 = LCELL( _EQ016);
_EQ016 = !_LC5_A29
# !_LC1_A35;
-- Node name is ':15'
-- Equation name is '_LC7_A19', type is buried
!_LC7_A19 = _LC7_A19~NOT;
_LC7_A19~NOT = LCELL( _EQ017);
_EQ017 = !_LC4_A19
# !_LC8_A35;
Project Information c:\max2work\vhdl\jsmk.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 25,733K
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