📄 jsmk.rpt
字号:
Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 8 0 17/0
Device-Specific Information: c:\max2work\vhdl\jsmk.rpt
jsmk
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
79 - - - -- INPUT G ^ 0 0 0 0 clk
78 - - - -- INPUT G ^ 0 0 0 0 clrn
80 - - - -- INPUT ^ 0 0 0 3 en
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\max2work\vhdl\jsmk.rpt
jsmk
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
197 - - - 28 OUTPUT 0 0 0 0 io_ds1
63 - - - 27 OUTPUT 0 0 0 0 io_ds2
70 - - - 22 OUTPUT 0 0 0 0 io_ds3
10 - - A -- OUTPUT 0 1 0 0 1d0
53 - - - 36 OUTPUT 0 1 0 0 1d1
149 - - A -- OUTPUT 0 1 0 0 1d2
207 - - - 35 OUTPUT 0 1 0 0 1d3
208 - - - 36 OUTPUT 0 1 0 0 1d4
11 - - A -- OUTPUT 0 1 0 0 1d5
8 - - A -- OUTPUT 0 1 0 0 1d6
9 - - A -- OUTPUT 0 1 0 0 1d7
74 - - - 20 OUTPUT 0 1 0 0 2d0
147 - - A -- OUTPUT 0 1 0 0 2d1
148 - - A -- OUTPUT 0 1 0 0 2d2
73 - - - 20 OUTPUT 0 1 0 0 2d3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\max2work\vhdl\jsmk.rpt
jsmk
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - A 35 OR2 0 2 0 5 :8
- 7 - A 19 OR2 ! 0 2 0 7 :15
- 5 - A 29 DFFE + 1 1 1 4 |74161:1|f74161:sub|QA (|74161:1|f74161:sub|:9)
- 2 - A 35 DFFE + 1 2 1 1 |74161:1|f74161:sub|QB (|74161:1|f74161:sub|:87)
- 6 - A 35 AND2 1 2 0 2 |74161:1|f74161:sub|:96
- 3 - A 35 DFFE + 0 2 1 1 |74161:1|f74161:sub|QC (|74161:1|f74161:sub|:99)
- 1 - A 35 DFFE + 0 3 1 3 |74161:1|f74161:sub|QD (|74161:1|f74161:sub|:110)
- 8 - A 35 DFFE + 0 2 1 3 |74161:2|f74161:sub|QA (|74161:2|f74161:sub|:9)
- 7 - A 35 DFFE + 0 3 1 1 |74161:2|f74161:sub|QB (|74161:2|f74161:sub|:87)
- 5 - A 35 AND2 0 4 0 2 |74161:2|f74161:sub|:96
- 3 - A 19 DFFE + 0 2 1 1 |74161:2|f74161:sub|QC (|74161:2|f74161:sub|:99)
- 4 - A 19 DFFE + 0 3 1 1 |74161:2|f74161:sub|QD (|74161:2|f74161:sub|:110)
- 2 - A 19 DFFE + 0 2 1 4 |74161:14|f74161:sub|QA (|74161:14|f74161:sub|:9)
- 6 - A 19 DFFE + 0 3 1 1 |74161:14|f74161:sub|QB (|74161:14|f74161:sub|:87)
- 5 - A 19 AND2 0 3 0 2 |74161:14|f74161:sub|:96
- 8 - A 19 DFFE + 0 3 1 1 |74161:14|f74161:sub|QC (|74161:14|f74161:sub|:99)
- 1 - A 19 DFFE + 0 3 1 3 |74161:14|f74161:sub|QD (|74161:14|f74161:sub|:110)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: c:\max2work\vhdl\jsmk.rpt
jsmk
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 9/144( 6%) 0/ 72( 0%) 3/ 72( 4%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
36: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\max2work\vhdl\jsmk.rpt
jsmk
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 12 clk
Device-Specific Information: c:\max2work\vhdl\jsmk.rpt
jsmk
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 12 clrn
Device-Specific Information: c:\max2work\vhdl\jsmk.rpt
jsmk
** EQUATIONS **
clk : INPUT;
clrn : INPUT;
en : INPUT;
-- Node name is 'io_ds1'
-- Equation name is 'io_ds1', type is output
io_ds1 = VCC;
-- Node name is 'io_ds2'
-- Equation name is 'io_ds2', type is output
io_ds2 = VCC;
-- Node name is 'io_ds3'
-- Equation name is 'io_ds3', type is output
io_ds3 = VCC;
-- Node name is '1d0'
-- Equation name is '1d0', type is output
1d0 = _LC5_A29;
-- Node name is '1d1'
-- Equation name is '1d1', type is output
1d1 = _LC2_A35;
-- Node name is '1d2'
-- Equation name is '1d2', type is output
1d2 = _LC3_A35;
-- Node name is '1d3'
-- Equation name is '1d3', type is output
1d3 = _LC1_A35;
-- Node name is '1d4'
-- Equation name is '1d4', type is output
1d4 = _LC8_A35;
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