📄 fenpin1.rpt
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-- Node name is '|jsmk:80|74161:14|f74161:sub|:87' = '|jsmk:80|74161:14|f74161:sub|QB'
-- Equation name is '_LC5_C17', type is buried
_LC5_C17 = DFFE( _EQ014, _LC8_C10, 2, VCC, VCC);
_EQ014 = !_LC4_C17 & _LC5_C17
# !_LC2_C17 & _LC5_C17 & !_LC8_C17
# _LC2_C17 & _LC4_C17 & !_LC5_C17 & !_LC8_C17;
-- Node name is '|jsmk:80|74161:14|f74161:sub|:99' = '|jsmk:80|74161:14|f74161:sub|QC'
-- Equation name is '_LC6_C17', type is buried
_LC6_C17 = DFFE( _EQ015, _LC8_C10, 2, VCC, VCC);
_EQ015 = !_LC4_C17 & _LC6_C17 & !_LC7_C17
# _LC6_C17 & !_LC7_C17 & !_LC8_C17
# !_LC4_C17 & !_LC6_C17 & _LC7_C17
# !_LC6_C17 & _LC7_C17 & !_LC8_C17;
-- Node name is '|jsmk:80|74161:14|f74161:sub|:110' = '|jsmk:80|74161:14|f74161:sub|QD'
-- Equation name is '_LC8_C17', type is buried
_LC8_C17 = DFFE( _EQ016, _LC8_C10, 2, VCC, VCC);
_EQ016 = _LC6_C17 & _LC7_C17 & !_LC8_C17
# !_LC4_C17 & !_LC6_C17 & _LC8_C17
# !_LC4_C17 & !_LC7_C17 & _LC8_C17;
-- Node name is '|jsmk:80|74161:14|f74161:sub|:96'
-- Equation name is '_LC7_C17', type is buried
_LC7_C17 = LCELL( _EQ017);
_EQ017 = _LC1_C17 & _LC4_C17 & _LC5_C10 & _LC5_C17;
-- Node name is '|KAIGUAN:1|~25~1'
-- Equation name is '_LC6_C10', type is buried
-- synthesized logic cell
_LC6_C10 = LCELL( _EQ018);
_EQ018 = _LC1_C10 & !_LC3_C8 & 1
# _LC2_C10 & !_LC3_C8 & 1;
-- Node name is '|KAIGUAN:1|:25'
-- Equation name is '_LC4_C8', type is buried
_LC4_C8 = LCELL( _EQ019);
_EQ019 = _LC5_C8 & _LC6_C10
# _LC6_C10 & !_LC6_C17
# !_LC2_C8 & _LC6_C10;
-- Node name is '|KAIGUAN:10|:25'
-- Equation name is '_LC5_C14', type is buried
_LC5_C14 = LCELL( _EQ020);
_EQ020 = _LC4_C8 & 100;
-- Node name is '|TINGZHIMOKUAI:5|:41'
-- Equation name is '_LC3_C8', type is buried
!_LC3_C8 = _LC3_C8~NOT;
_LC3_C8~NOT = LCELL( _EQ021);
_EQ021 = !_LC4_C17
# !_LC8_C8
# !_LC1_C8
# !_LC5_C17;
-- Node name is '|TINGZHIMOKUAI:6|~41~1'
-- Equation name is '_LC5_C8', type is buried
-- synthesized logic cell
_LC5_C8 = LCELL( _EQ022);
_EQ022 = _LC8_C17 & !12
# !_LC8_C17 & 12
# _LC6_C8 & !13
# !_LC6_C8 & 13;
-- Node name is '|TINGZHIMOKUAI:7|~41~1'
-- Equation name is '_LC1_C10', type is buried
-- synthesized logic cell
_LC1_C10 = LCELL( _EQ023);
_EQ023 = _LC3_C17 & !20
# !_LC3_C17 & 20
# _LC1_C17 & !21
# !_LC1_C17 & 21;
-- Node name is '|TINGZHIMOKUAI:7|~41~2'
-- Equation name is '_LC2_C10', type is buried
-- synthesized logic cell
_LC2_C10 = LCELL( _EQ024);
_EQ024 = _LC5_C10 & !18
# !_LC5_C10 & 18
# _LC4_C10 & !19
# !_LC4_C10 & 19;
-- Node name is '|untitled3:4|:25'
-- Equation name is '_LC6_C14', type is buried
_LC6_C14 = LCELL( _EQ025);
_EQ025 = !_LC2_C14
# !_LC3_C14
# !_LC4_C14;
-- Node name is '|untitled3:4|74138:37|:15' = '|untitled3:4|74138:37|Y0N'
-- Equation name is '_LC1_C24', type is buried
!_LC1_C24 = _LC1_C24~NOT;
_LC1_C24~NOT = LCELL( _EQ026);
_EQ026 = !_LC2_C14 & !_LC3_C14 & !_LC4_C14;
-- Node name is '|untitled3:4|74138:37|:16' = '|untitled3:4|74138:37|Y1N'
-- Equation name is '_LC3_C24', type is buried
!_LC3_C24 = _LC3_C24~NOT;
_LC3_C24~NOT = LCELL( _EQ027);
_EQ027 = !_LC2_C14 & !_LC3_C14 & _LC4_C14;
-- Node name is '|untitled3:4|74138:37|:17' = '|untitled3:4|74138:37|Y2N'
-- Equation name is '_LC8_C24', type is buried
!_LC8_C24 = _LC8_C24~NOT;
_LC8_C24~NOT = LCELL( _EQ028);
_EQ028 = !_LC2_C14 & _LC3_C14 & !_LC4_C14;
-- Node name is '|untitled3:4|74138:37|:18' = '|untitled3:4|74138:37|Y3N'
-- Equation name is '_LC7_C24', type is buried
!_LC7_C24 = _LC7_C24~NOT;
_LC7_C24~NOT = LCELL( _EQ029);
_EQ029 = !_LC2_C14 & _LC3_C14 & _LC4_C14;
-- Node name is '|untitled3:4|74138:37|:19' = '|untitled3:4|74138:37|Y4N'
-- Equation name is '_LC2_C34', type is buried
!_LC2_C34 = _LC2_C34~NOT;
_LC2_C34~NOT = LCELL( _EQ030);
_EQ030 = _LC2_C14 & !_LC3_C14 & !_LC4_C14;
-- Node name is '|untitled3:4|74138:37|:20' = '|untitled3:4|74138:37|Y5N'
-- Equation name is '_LC3_C34', type is buried
!_LC3_C34 = _LC3_C34~NOT;
_LC3_C34~NOT = LCELL( _EQ031);
_EQ031 = _LC2_C14 & !_LC3_C14 & _LC4_C14;
-- Node name is '|untitled3:4|74138:37|:21' = '|untitled3:4|74138:37|Y6N'
-- Equation name is '_LC4_C24', type is buried
!_LC4_C24 = _LC4_C24~NOT;
_LC4_C24~NOT = LCELL( _EQ032);
_EQ032 = _LC2_C14 & _LC3_C14 & !_LC4_C14;
-- Node name is '|untitled3:4|74161:1|f74161:sub|:9' = '|untitled3:4|74161:1|f74161:sub|QA'
-- Equation name is '_LC4_C14', type is buried
_LC4_C14 = DFFE(!_LC4_C14, _LC5_C14, VCC, VCC, VCC);
-- Node name is '|untitled3:4|74161:1|f74161:sub|:87' = '|untitled3:4|74161:1|f74161:sub|QB'
-- Equation name is '_LC3_C14', type is buried
_LC3_C14 = DFFE( _EQ033, _LC5_C14, VCC, VCC, VCC);
_EQ033 = _LC3_C14 & !_LC4_C14 & _LC6_C14
# !_LC3_C14 & _LC4_C14 & _LC6_C14;
-- Node name is '|untitled3:4|74161:1|f74161:sub|:99' = '|untitled3:4|74161:1|f74161:sub|QC'
-- Equation name is '_LC2_C14', type is buried
_LC2_C14 = DFFE( _EQ034, _LC5_C14, VCC, VCC, VCC);
_EQ034 = _LC2_C14 & !_LC3_C14 & _LC6_C14
# _LC2_C14 & !_LC4_C14 & _LC6_C14
# !_LC2_C14 & _LC3_C14 & _LC4_C14 & _LC6_C14;
Project Information d:\vhd\fenpin1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 25,039K
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