📄 fenpin1.rpt
字号:
C17 8/ 8(100%) 4/ 8( 50%) 6/ 8( 75%) 1/2 1/2 4/22( 18%)
C24 5/ 8( 62%) 4/ 8( 50%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C34 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 3/22( 13%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 35/141 ( 24%)
Total logic cells used: 39/1728 ( 2%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.12/4 ( 78%)
Total fan-in: 122/6912 ( 1%)
Total input pins required: 9
Total input I/O cell registers required: 0
Total output pins required: 26
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 39
Total flipflops required: 19
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 4/1728 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 8 0 8 0 0 0 8 0 0 8 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 2 0 0 39/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 0 0 0 0 8 0 8 0 0 0 8 0 0 8 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 2 0 0 39/0
Device-Specific Information: d:\vhd\fenpin1.rpt
fenpin1
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
75 - - - 19 INPUT ^ 0 0 0 1 1
90 - - - 12 INPUT ^ 0 0 0 12 2
83 - - - 17 INPUT ^ 0 0 0 1 12
85 - - - 16 INPUT ^ 0 0 0 1 13
86 - - - 15 INPUT ^ 0 0 0 1 18
87 - - - 14 INPUT ^ 0 0 0 1 19
88 - - - 14 INPUT ^ 0 0 0 1 20
89 - - - 13 INPUT ^ 0 0 0 1 21
179 - - - 17 INPUT ^ 0 0 0 5 100
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\vhd\fenpin1.rpt
fenpin1
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
187 - - - 20 OUTPUT 0 0 0 0 3
189 - - - 21 OUTPUT 0 0 0 0 4
190 - - - 22 OUTPUT 0 0 0 0 5
142 - - B -- OUTPUT 0 1 0 0 22
141 - - B -- OUTPUT 0 1 0 0 23
128 - - D -- OUTPUT 0 1 0 0 24
131 - - C -- OUTPUT 0 1 0 0 25
127 - - D -- OUTPUT 0 1 0 0 26
140 - - B -- OUTPUT 0 1 0 0 27
139 - - B -- OUTPUT 0 1 0 0 28
132 - - C -- OUTPUT 0 1 0 0 29
133 - - C -- OUTPUT 0 1 0 0 30
134 - - C -- OUTPUT 0 1 0 0 31
135 - - C -- OUTPUT 0 1 0 0 32
136 - - C -- OUTPUT 0 1 0 0 33
94 - - - 09 OUTPUT 0 0 0 0 34
95 - - - 09 OUTPUT 0 0 0 0 35
96 - - - 08 OUTPUT 0 0 0 0 36
12 - - B -- OUTPUT 0 1 0 0 38
13 - - B -- OUTPUT 0 1 0 0 39
14 - - B -- OUTPUT 0 1 0 0 40
15 - - B -- OUTPUT 0 1 0 0 41
17 - - C -- OUTPUT 0 1 0 0 42
18 - - C -- OUTPUT 0 1 0 0 43
19 - - C -- OUTPUT 0 1 0 0 44
24 - - C -- OUTPUT 0 1 0 0 45
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\vhd\fenpin1.rpt
fenpin1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - C 14 DFFE 1 1 0 1 |fenpin:3|74195:1|Q0 (|fenpin:3|74195:1|:15)
- 8 - C 14 DFFE 1 1 0 1 |fenpin:3|74195:1|Q1 (|fenpin:3|74195:1|:16)
- 1 - C 14 DFFE 1 1 0 1 |fenpin:3|74195:1|Q2 (|fenpin:3|74195:1|:17)
- 8 - C 10 DFFE 1 1 0 13 |fenpin:3|74195:1|Q3 (|fenpin:3|74195:1|:18)
- 7 - C 10 OR2 ! 0 2 0 6 |jsmk:80|:7
- 2 - C 17 AND2 0 2 0 1 |jsmk:80|:15
- 2 - C 08 DFFE 1 3 1 5 |jsmk:80|74161:1|f74161:sub|QA (|jsmk:80|74161:1|f74161:sub|:9)
- 1 - C 08 DFFE 1 4 1 2 |jsmk:80|74161:1|f74161:sub|QB (|jsmk:80|74161:1|f74161:sub|:87)
- 7 - C 08 AND2 0 3 0 2 |jsmk:80|74161:1|f74161:sub|:96
- 8 - C 08 DFFE 1 3 1 2 |jsmk:80|74161:1|f74161:sub|QC (|jsmk:80|74161:1|f74161:sub|:99)
- 6 - C 08 DFFE 1 4 1 3 |jsmk:80|74161:1|f74161:sub|QD (|jsmk:80|74161:1|f74161:sub|:110)
- 5 - C 10 DFFE 1 3 1 8 |jsmk:80|74161:2|f74161:sub|QA (|jsmk:80|74161:2|f74161:sub|:9)
- 4 - C 10 DFFE 1 4 1 2 |jsmk:80|74161:2|f74161:sub|QB (|jsmk:80|74161:2|f74161:sub|:87)
- 3 - C 10 AND2 0 4 0 2 |jsmk:80|74161:2|f74161:sub|:96
- 3 - C 17 DFFE 1 4 1 2 |jsmk:80|74161:2|f74161:sub|QC (|jsmk:80|74161:2|f74161:sub|:99)
- 1 - C 17 DFFE 1 4 1 7 |jsmk:80|74161:2|f74161:sub|QD (|jsmk:80|74161:2|f74161:sub|:110)
- 4 - C 17 DFFE 1 4 1 5 |jsmk:80|74161:14|f74161:sub|QA (|jsmk:80|74161:14|f74161:sub|:9)
- 5 - C 17 DFFE 1 4 1 2 |jsmk:80|74161:14|f74161:sub|QB (|jsmk:80|74161:14|f74161:sub|:87)
- 7 - C 17 AND2 0 4 0 2 |jsmk:80|74161:14|f74161:sub|:96
- 6 - C 17 DFFE 1 4 1 2 |jsmk:80|74161:14|f74161:sub|QC (|jsmk:80|74161:14|f74161:sub|:99)
- 8 - C 17 DFFE 1 4 1 4 |jsmk:80|74161:14|f74161:sub|QD (|jsmk:80|74161:14|f74161:sub|:110)
- 6 - C 10 OR2 s 1 3 0 1 |KAIGUAN:1|~25~1
- 4 - C 08 OR2 0 4 0 4 |KAIGUAN:1|:25
- 5 - C 14 AND2 1 1 0 3 |KAIGUAN:10|:25
- 3 - C 08 OR2 ! 0 4 0 1 |TINGZHIMOKUAI:5|:41
- 5 - C 08 OR2 s 2 2 0 1 |TINGZHIMOKUAI:6|~41~1
- 1 - C 10 OR2 s 2 2 0 1 |TINGZHIMOKUAI:7|~41~1
- 2 - C 10 OR2 s 2 2 0 1 |TINGZHIMOKUAI:7|~41~2
- 6 - C 14 OR2 0 3 1 2 |untitled3:4|:25
- 1 - C 24 AND2 ! 0 3 1 0 |untitled3:4|74138:37|Y0N (|untitled3:4|74138:37|:15)
- 3 - C 24 AND2 ! 0 3 1 0 |untitled3:4|74138:37|Y1N (|untitled3:4|74138:37|:16)
- 8 - C 24 AND2 ! 0 3 1 0 |untitled3:4|74138:37|Y2N (|untitled3:4|74138:37|:17)
- 7 - C 24 AND2 ! 0 3 1 0 |untitled3:4|74138:37|Y3N (|untitled3:4|74138:37|:18)
- 2 - C 34 AND2 ! 0 3 1 0 |untitled3:4|74138:37|Y4N (|untitled3:4|74138:37|:19)
- 3 - C 34 AND2 ! 0 3 1 0 |untitled3:4|74138:37|Y5N (|untitled3:4|74138:37|:20)
- 4 - C 24 AND2 ! 0 3 1 0 |untitled3:4|74138:37|Y6N (|untitled3:4|74138:37|:21)
- 4 - C 14 DFFE 0 1 0 10 |untitled3:4|74161:1|f74161:sub|QA (|untitled3:4|74161:1|f74161:sub|:9)
- 3 - C 14 DFFE 0 3 0 9 |untitled3:4|74161:1|f74161:sub|QB (|untitled3:4|74161:1|f74161:sub|:87)
- 2 - C 14 DFFE 0 4 0 8 |untitled3:4|74161:1|f74161:sub|QC (|untitled3:4|74161:1|f74161:sub|:99)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\vhd\fenpin1.rpt
fenpin1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 4/ 72( 5%) 4/ 72( 5%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 19/144( 13%) 15/ 72( 20%) 3/ 72( 4%) 0/16( 0%) 10/16( 62%) 0/16( 0%)
D: 0/144( 0%) 2/ 72( 2%) 0/ 72( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 5/24( 20%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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