📄 stm32f2xx_dma.h
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#define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000)
#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \
((BURST) == DMA_MemoryBurst_INC4) || \
((BURST) == DMA_MemoryBurst_INC8) || \
((BURST) == DMA_MemoryBurst_INC16))
/**
* @}
*/
/** @defgroup DMA_peripheral_burst
* @{
*/
#define DMA_PeripheralBurst_Single ((uint32_t)0x00000000)
#define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000)
#define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000)
#define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000)
#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \
((BURST) == DMA_PeripheralBurst_INC4) || \
((BURST) == DMA_PeripheralBurst_INC8) || \
((BURST) == DMA_PeripheralBurst_INC16))
/**
* @}
*/
/** @defgroup DMA_fifo_status_level
* @{
*/
#define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3)
#define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3)
#define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3)
#define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3)
#define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3)
#define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3)
#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \
((STATUS) == DMA_FIFOStatus_HalfFull) || \
((STATUS) == DMA_FIFOStatus_1QuarterFull) || \
((STATUS) == DMA_FIFOStatus_3QuartersFull) || \
((STATUS) == DMA_FIFOStatus_Full) || \
((STATUS) == DMA_FIFOStatus_Empty))
/**
* @}
*/
/** @defgroup DMA_flags_definition
* @{
*/
#define DMA_FLAG_FEIF0 ((uint32_t)0x10800001)
#define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004)
#define DMA_FLAG_TEIF0 ((uint32_t)0x10000008)
#define DMA_FLAG_HTIF0 ((uint32_t)0x10000010)
#define DMA_FLAG_TCIF0 ((uint32_t)0x10000020)
#define DMA_FLAG_FEIF1 ((uint32_t)0x10000040)
#define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100)
#define DMA_FLAG_TEIF1 ((uint32_t)0x10000200)
#define DMA_FLAG_HTIF1 ((uint32_t)0x10000400)
#define DMA_FLAG_TCIF1 ((uint32_t)0x10000800)
#define DMA_FLAG_FEIF2 ((uint32_t)0x10010000)
#define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000)
#define DMA_FLAG_TEIF2 ((uint32_t)0x10080000)
#define DMA_FLAG_HTIF2 ((uint32_t)0x10100000)
#define DMA_FLAG_TCIF2 ((uint32_t)0x10200000)
#define DMA_FLAG_FEIF3 ((uint32_t)0x10400000)
#define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000)
#define DMA_FLAG_TEIF3 ((uint32_t)0x12000000)
#define DMA_FLAG_HTIF3 ((uint32_t)0x14000000)
#define DMA_FLAG_TCIF3 ((uint32_t)0x18000000)
#define DMA_FLAG_FEIF4 ((uint32_t)0x20000001)
#define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004)
#define DMA_FLAG_TEIF4 ((uint32_t)0x20000008)
#define DMA_FLAG_HTIF4 ((uint32_t)0x20000010)
#define DMA_FLAG_TCIF4 ((uint32_t)0x20000020)
#define DMA_FLAG_FEIF5 ((uint32_t)0x20000040)
#define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100)
#define DMA_FLAG_TEIF5 ((uint32_t)0x20000200)
#define DMA_FLAG_HTIF5 ((uint32_t)0x20000400)
#define DMA_FLAG_TCIF5 ((uint32_t)0x20000800)
#define DMA_FLAG_FEIF6 ((uint32_t)0x20010000)
#define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000)
#define DMA_FLAG_TEIF6 ((uint32_t)0x20080000)
#define DMA_FLAG_HTIF6 ((uint32_t)0x20100000)
#define DMA_FLAG_TCIF6 ((uint32_t)0x20200000)
#define DMA_FLAG_FEIF7 ((uint32_t)0x20400000)
#define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000)
#define DMA_FLAG_TEIF7 ((uint32_t)0x22000000)
#define DMA_FLAG_HTIF7 ((uint32_t)0x24000000)
#define DMA_FLAG_TCIF7 ((uint32_t)0x28000000)
#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \
(((FLAG) & 0xC082F082) == 0x00) && ((FLAG) != 0x00))
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \
((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \
((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \
((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \
((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \
((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \
((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \
((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \
((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \
((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \
((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \
((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \
((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \
((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \
((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \
((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \
((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \
((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \
((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \
((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7))
/**
* @}
*/
/** @defgroup DMA_interrupt_enable_definitions
* @{
*/
#define DMA_IT_TC ((uint32_t)0x00000010)
#define DMA_IT_HT ((uint32_t)0x00000008)
#define DMA_IT_TE ((uint32_t)0x00000004)
#define DMA_IT_DME ((uint32_t)0x00000002)
#define DMA_IT_FE ((uint32_t)0x00000080)
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00))
/**
* @}
*/
/** @defgroup DMA_interrupts_definitions
* @{
*/
#define DMA_IT_FEIF0 ((uint32_t)0x90000001)
#define DMA_IT_DMEIF0 ((uint32_t)0x10001004)
#define DMA_IT_TEIF0 ((uint32_t)0x10002008)
#define DMA_IT_HTIF0 ((uint32_t)0x10004010)
#define DMA_IT_TCIF0 ((uint32_t)0x10008020)
#define DMA_IT_FEIF1 ((uint32_t)0x90000040)
#define DMA_IT_DMEIF1 ((uint32_t)0x10001100)
#define DMA_IT_TEIF1 ((uint32_t)0x10002200)
#define DMA_IT_HTIF1 ((uint32_t)0x10004400)
#define DMA_IT_TCIF1 ((uint32_t)0x10008800)
#define DMA_IT_FEIF2 ((uint32_t)0x90010000)
#define DMA_IT_DMEIF2 ((uint32_t)0x10041000)
#define DMA_IT_TEIF2 ((uint32_t)0x10082000)
#define DMA_IT_HTIF2 ((uint32_t)0x10104000)
#define DMA_IT_TCIF2 ((uint32_t)0x10208000)
#define DMA_IT_FEIF3 ((uint32_t)0x90400000)
#define DMA_IT_DMEIF3 ((uint32_t)0x11001000)
#define DMA_IT_TEIF3 ((uint32_t)0x12002000)
#define DMA_IT_HTIF3 ((uint32_t)0x14004000)
#define DMA_IT_TCIF3 ((uint32_t)0x18008000)
#define DMA_IT_FEIF4 ((uint32_t)0xA0000001)
#define DMA_IT_DMEIF4 ((uint32_t)0x20001004)
#define DMA_IT_TEIF4 ((uint32_t)0x20002008)
#define DMA_IT_HTIF4 ((uint32_t)0x20004010)
#define DMA_IT_TCIF4 ((uint32_t)0x20008020)
#define DMA_IT_FEIF5 ((uint32_t)0xA0000040)
#define DMA_IT_DMEIF5 ((uint32_t)0x20001100)
#define DMA_IT_TEIF5 ((uint32_t)0x20002200)
#define DMA_IT_HTIF5 ((uint32_t)0x20004400)
#define DMA_IT_TCIF5 ((uint32_t)0x20008800)
#define DMA_IT_FEIF6 ((uint32_t)0xA0010000)
#define DMA_IT_DMEIF6 ((uint32_t)0x20041000)
#define DMA_IT_TEIF6 ((uint32_t)0x20082000)
#define DMA_IT_HTIF6 ((uint32_t)0x20104000)
#define DMA_IT_TCIF6 ((uint32_t)0x20208000)
#define DMA_IT_FEIF7 ((uint32_t)0xA0400000)
#define DMA_IT_DMEIF7 ((uint32_t)0x21001000)
#define DMA_IT_TEIF7 ((uint32_t)0x22002000)
#define DMA_IT_HTIF7 ((uint32_t)0x24004000)
#define DMA_IT_TCIF7 ((uint32_t)0x28008000)
#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \
(((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \
(((IT) & 0x40820082) == 0x00))
#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \
((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \
((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \
((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \
((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \
((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \
((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \
((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \
((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \
((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \
((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \
((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \
((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \
((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \
((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \
((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \
((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \
((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \
((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \
((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7))
/**
* @}
*/
/** @defgroup DMA_peripheral_increment_offset
* @{
*/
#define DMA_PINCOS_Psize ((uint32_t)0x00000000)
#define DMA_PINCOS_WordAligned ((uint32_t)0x00008000)
#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \
((SIZE) == DMA_PINCOS_WordAligned))
/**
* @}
*/
/** @defgroup DMA_flow_controller_definitions
* @{
*/
#define DMA_FlowCtrl_Memory ((uint32_t)0x00000000)
#define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020)
#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \
((CTRL) == DMA_FlowCtrl_Peripheral))
/**
* @}
*/
/** @defgroup DMA_memory_targets_definitions
* @{
*/
#define DMA_Memory_0 ((uint32_t)0x00000000)
#define DMA_Memory_1 ((uint32_t)0x00080000)
#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Function used to set the DMA configuration to the default reset state *****/
void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx);
/* Initialization and Configuration functions *********************************/
void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct);
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
/* Optional Configuration functions *******************************************/
void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos);
void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl);
/* Data Counter functions *****************************************************/
void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
/* Double Buffer mode functions ***********************************************/
void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
uint32_t DMA_CurrentMemory);
void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
uint32_t DMA_MemoryTarget);
uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
/* Interrupts and flags management functions **********************************/
FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F2xx_DMA_H */
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
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