fft_32k.map.qmsg

32k点的fft程序.非常不错,编译已经实现,还是很好的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 25 13:19:59 2006 " "Info: Processing started: Tue Apr 25 13:19:59 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off FFT_32K -c FFT_32K " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FFT_32K -c FFT_32K" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../source/clk_pll.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../source/clk_pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_pll " "Info: Found entity 1: clk_pll" {  } { { "../source/clk_pll.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/clk_pll.v" 36 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../source/twiddle_rom_add.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../source/twiddle_rom_add.v" { { "Info" "ISGN_ENTITY_NAME" "1 twiddle_rom_add " "Info: Found entity 1: twiddle_rom_add" {  } { { "../source/twiddle_rom_add.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/twiddle_rom_add.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../source/comb_final_fft_res.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../source/comb_final_fft_res.v" { { "Info" "ISGN_ENTITY_NAME" "1 comb_final_fft_res " "Info: Found entity 1: comb_final_fft_res" {  } { { "../source/comb_final_fft_res.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/comb_final_fft_res.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../source/combine_fft.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../source/combine_fft.v" { { "Info" "ISGN_ENTITY_NAME" "1 combine_fft " "Info: Found entity 1: combine_fft" {  } { { "../source/combine_fft.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/combine_fft.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../source/fft_32K.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../source/fft_32K.v" { { "Info" "ISGN_ENTITY_NAME" "1 fft_32K " "Info: Found entity 1: fft_32K" {  } { { "../source/fft_32K.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/fft_32K.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../source/fft_small.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../source/fft_small.v" { { "Info" "ISGN_ENTITY_NAME" "1 fft_small " "Info: Found entity 1: fft_small" {  } { { "../source/fft_small.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/fft_small.v" 33 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../source/mram_buf.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../source/mram_buf.v" { { "Info" "ISGN_ENTITY_NAME" "1 mram_buf " "Info: Found entity 1: mram_buf" {  } { { "../source/mram_buf.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/mram_buf.v" 36 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../source/mul_fft_bot_tf.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../source/mul_fft_bot_tf.v" { { "Info" "ISGN_ENTITY_NAME" "1 mul_fft_bot_tf " "Info: Found entity 1: mul_fft_bot_tf" {  } { { "../source/mul_fft_bot_tf.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/mul_fft_bot_tf.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../source/mult_add.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../source/mult_add.v" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add " "Info: Found entity 1: mult_add" {  } { { "../source/mult_add.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/mult_add.v" 36 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../source/parse_fft_input.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../source/parse_fft_input.v" { { "Info" "ISGN_ENTITY_NAME" "1 parse_fft_input " "Info: Found entity 1: parse_fft_input" {  } { { "../source/parse_fft_input.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/parse_fft_input.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../source/scale_fft_res.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../source/scale_fft_res.v" { { "Info" "ISGN_ENTITY_NAME" "1 scale_fft_res " "Info: Found entity 1: scale_fft_res" {  } { { "../source/scale_fft_res.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/scale_fft_res.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "C:/software/altera/MegaCore/fft-v2.1.3/lib/fft_pack.vhd " "Warning: Can't analyze file -- file C:/software/altera/MegaCore/fft-v2.1.3/lib/fft_pack.vhd is missing" {  } {  } 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "C:/altera/design_example/fft_32K/source/fft_small.v " "Warning: Can't analyze file -- file C:/altera/design_example/fft_32K/source/fft_small.v is missing" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "fft_32K " "Info: Elaborating entity \"fft_32K\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_pll clk_pll:clk_pll_inst " "Info: Elaborating entity \"clk_pll\" for hierarchy \"clk_pll:clk_pll_inst\"" {  } { { "../source/fft_32K.v" "clk_pll_inst" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/fft_32K.v" 85 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus50/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/altpll.tdf" 363 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll clk_pll:clk_pll_inst\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"clk_pll:clk_pll_inst\|altpll:altpll_component\"" {  } { { "../source/clk_pll.v" "altpll_component" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/clk_pll.v" 83 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "parse_fft_input parse_fft_input:parse_fft_input_inst " "Info: Elaborating entity \"parse_fft_input\" for hierarchy \"parse_fft_input:parse_fft_input_inst\"" {  } { { "../source/fft_32K.v" "parse_fft_input_inst" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/fft_32K.v" 107 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 parse_fft_input.v(105) " "Warning: Verilog HDL assignment warning at parse_fft_input.v(105): truncated value with size 32 to match size of target (1)" {  } { { "../source/parse_fft_input.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/parse_fft_input.v" 105 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 parse_fft_input.v(138) " "Warning: Verilog HDL assignment warning at parse_fft_input.v(138): truncated value with size 32 to match size of target (16)" {  } { { "../source/parse_fft_input.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/parse_fft_input.v" 138 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 parse_fft_input.v(139) " "Warning: Verilog HDL assignment warning at parse_fft_input.v(139): truncated value with size 32 to match size of target (16)" {  } { { "../source/parse_fft_input.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/parse_fft_input.v" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 parse_fft_input.v(140) " "Warning: Verilog HDL assignment warning at parse_fft_input.v(140): truncated value with size 32 to match size of target (16)" {  } { { "../source/parse_fft_input.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/parse_fft_input.v" 140 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 parse_fft_input.v(141) " "Warning: Verilog HDL assignment warning at parse_fft_input.v(141): truncated value with size 32 to match size of target (16)" {  } { { "../source/parse_fft_input.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/parse_fft_input.v" 141 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 parse_fft_input.v(142) " "Warning: Verilog HDL assignment warning at parse_fft_input.v(142): truncated value with size 32 to match size of target (16)" {  } { { "../source/parse_fft_input.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/parse_fft_input.v" 142 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 parse_fft_input.v(143) " "Warning: Verilog HDL assignment warning at parse_fft_input.v(143): truncated value with size 32 to match size of target (16)" {  } { { "../source/parse_fft_input.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/parse_fft_input.v" 143 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 parse_fft_input.v(162) " "Warning: Verilog HDL assignment warning at parse_fft_input.v(162): truncated value with size 32 to match size of target (16)" {  } { { "../source/parse_fft_input.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/parse_fft_input.v" 162 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 parse_fft_input.v(163) " "Warning: Verilog HDL assignment warning at parse_fft_input.v(163): truncated value with size 32 to match size of target (16)" {  } { { "../source/parse_fft_input.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/parse_fft_input.v" 163 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 parse_fft_input.v(164) " "Warning: Verilog HDL assignment warning at parse_fft_input.v(164): truncated value with size 32 to match size of target (16)" {  } { { "../source/parse_fft_input.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/parse_fft_input.v" 164 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 parse_fft_input.v(165) " "Warning: Verilog HDL assignment warning at parse_fft_input.v(165): truncated value with size 32 to match size of target (16)" {  } { { "../source/parse_fft_input.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/parse_fft_input.v" 165 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 parse_fft_input.v(166) " "Warning: Verilog HDL assignment warning at parse_fft_input.v(166): truncated value with size 32 to match size of target (16)" {  } { { "../source/parse_fft_input.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/parse_fft_input.v" 166 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 parse_fft_input.v(167) " "Warning: Verilog HDL assignment warning at parse_fft_input.v(167): truncated value with size 32 to match size of target (16)" {  } { { "../source/parse_fft_input.v" "" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/parse_fft_input.v" 167 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fft_small fft_small:fft_small_top " "Info: Elaborating entity \"fft_small\" for hierarchy \"fft_small:fft_small_top\"" {  } { { "../source/fft_32K.v" "fft_small_top" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/fft_32K.v" 128 -1 0 } }  } 0}
{ "Error" "ESGN_ENTITY_IS_MISSING" "asj_fft_dualstream_inst asj_fft_dualstream " "Error: Node instance \"asj_fft_dualstream_inst\" instantiates undefined entity \"asj_fft_dualstream\"" {  } { { "../source/fft_small.v" "asj_fft_dualstream_inst" { Text "C:/Documents and Settings/All Users/Documents/文件/fft_32K/altera/design_example/fft_32K/source/fft_small.v" 83 -1 0 } }  } 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  15 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 15 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Tue Apr 25 13:20:01 2006 " "Error: Processing ended: Tue Apr 25 13:20:01 2006" {  } {  } 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Error: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}