📄 drvtimer.lst
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N#define INT_FAST64_MAX __ESCAPE__(9223372036854775807ll)
N
N /* maximum values of fastest minimum-width unsigned integer types */
N#define UINT_FAST8_MAX 4294967295u
N#define UINT_FAST16_MAX 4294967295u
N#define UINT_FAST32_MAX 4294967295u
N#define UINT_FAST64_MAX __ESCAPE__(18446744073709551615ull)
N
N /* 7.18.2.4 */
N
N /* minimum value of pointer-holding signed integer type */
N#define INTPTR_MIN (~0x7fffffff)
N
N /* maximum value of pointer-holding signed integer type */
N#define INTPTR_MAX 2147483647
N
N /* maximum value of pointer-holding unsigned integer type */
N#define UINTPTR_MAX 4294967295u
N
N /* 7.18.2.5 */
N
N /* minimum value of greatest-width signed integer type */
N#define INTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll)
N
N /* maximum value of greatest-width signed integer type */
N#define INTMAX_MAX __ESCAPE__(9223372036854775807ll)
N
N /* maximum value of greatest-width unsigned integer type */
N#define UINTMAX_MAX __ESCAPE__(18446744073709551615ull)
N
N /* 7.18.3 */
N
N /* limits of ptrdiff_t */
N#define PTRDIFF_MIN (~0x7fffffff)
N#define PTRDIFF_MAX 2147483647
N
N /* limits of sig_atomic_t */
N#define SIG_ATOMIC_MIN (~0x7fffffff)
N#define SIG_ATOMIC_MAX 2147483647
N
N /* limit of size_t */
N#define SIZE_MAX 4294967295u
N
N /* limits of wchar_t */
N /* NB we have to undef and redef because they're defined in both
N * stdint.h and wchar.h */
N#undef WCHAR_MIN
N#undef WCHAR_MAX
N
N#if defined(__WCHAR32)
X#if 0L
S #define WCHAR_MIN 0
S #define WCHAR_MAX 0xffffffffU
N#else
N #define WCHAR_MIN 0
N #define WCHAR_MAX 65535
N#endif
N
N /* limits of wint_t */
N#define WINT_MIN (~0x7fffffff)
N#define WINT_MAX 2147483647
N
N#endif /* __STDC_LIMIT_MACROS */
N
N#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS)
X#if !0L || 0L
N
N /* 7.18.4.1 macros for minimum-width integer constants */
N#define INT8_C(x) (x)
N#define INT16_C(x) (x)
N#define INT32_C(x) (x)
N#define INT64_C(x) __ESCAPE__(x ## ll)
N
N#define UINT8_C(x) (x ## u)
N#define UINT16_C(x) (x ## u)
N#define UINT32_C(x) (x ## u)
N#define UINT64_C(x) __ESCAPE__(x ## ull)
N
N /* 7.18.4.2 macros for greatest-width integer constants */
N#define INTMAX_C(x) __ESCAPE__(x ## ll)
N#define UINTMAX_C(x) __ESCAPE__(x ## ull)
N
N#endif /* __STDC_CONSTANT_MACROS */
N
N #ifdef __cplusplus
S } /* extern "C" */
S } /* namespace std */
N #endif /* __cplusplus */
N #endif /* __STDINT_DECLS */
N
N #ifdef __cplusplus
S #ifndef __STDINT_NO_EXPORTS
S using ::std::int8_t;
S using ::std::int16_t;
S using ::std::int32_t;
S using ::std::int64_t;
S using ::std::uint8_t;
S using ::std::uint16_t;
S using ::std::uint32_t;
S using ::std::uint64_t;
S using ::std::int_least8_t;
S using ::std::int_least16_t;
S using ::std::int_least32_t;
S using ::std::int_least64_t;
S using ::std::uint_least8_t;
S using ::std::uint_least16_t;
S using ::std::uint_least32_t;
S using ::std::uint_least64_t;
S using ::std::int_fast8_t;
S using ::std::int_fast16_t;
S using ::std::int_fast32_t;
S using ::std::int_fast64_t;
S using ::std::uint_fast8_t;
S using ::std::uint_fast16_t;
S using ::std::uint_fast32_t;
S using ::std::uint_fast64_t;
S using ::std::intptr_t;
S using ::std::uintptr_t;
S using ::std::intmax_t;
S using ::std::uintmax_t;
S #endif
N #endif /* __cplusplus */
N
N#endif /* __stdint_h */
N
N/* end of stdint.h */
N
N
L 56 "..\Lib\CMSIS\CM0\CoreSupport\core_cm0.h" 2
N
N#if defined (__ICCARM__)
X#if 0L
S #include <intrinsics.h> /* IAR Intrinsics */
N#endif
N
N
N#ifndef __NVIC_PRIO_BITS
S #define __NVIC_PRIO_BITS 2 /*!< standard definition for NVIC Priority Bits */
N#endif
N
N
N
N
N/**
N * IO definitions
N *
N * define access restrictions to peripheral registers
N */
N
N#ifdef __cplusplus
S #define __I volatile /*!< defines 'read only' permissions */
N#else
N #define __I volatile const /*!< defines 'read only' permissions */
N#endif
N#define __O volatile /*!< defines 'write only' permissions */
N#define __IO volatile /*!< defines 'read / write' permissions */
N
N
N
N/*******************************************************************************
N * Register Abstraction
N ******************************************************************************/
N/** @addtogroup CMSIS_CM0_core_register CMSIS CM0 Core Register
N @{
N*/
N
N
N/** @addtogroup CMSIS_CM0_NVIC CMSIS CM0 NVIC
N memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
N @{
N */
Ntypedef struct
N{
N __IO uint32_t ISER[1]; /*!< (Offset: 0x000) Interrupt Set Enable Register */
X volatile uint32_t ISER[1];
N uint32_t RESERVED0[31];
N __IO uint32_t ICER[1]; /*!< (Offset: 0x080) Interrupt Clear Enable Register */
X volatile uint32_t ICER[1];
N uint32_t RSERVED1[31];
N __IO uint32_t ISPR[1]; /*!< (Offset: 0x100) Interrupt Set Pending Register */
X volatile uint32_t ISPR[1];
N uint32_t RESERVED2[31];
N __IO uint32_t ICPR[1]; /*!< (Offset: 0x180) Interrupt Clear Pending Register */
X volatile uint32_t ICPR[1];
N uint32_t RESERVED3[31];
N uint32_t RESERVED4[64];
N __IO uint32_t IPR[8]; /*!< (Offset: 0x3EC) Interrupt Priority Register */
X volatile uint32_t IPR[8];
N} NVIC_Type;
N/*@}*/ /* end of group CMSIS_CM0_NVIC */
N
N
N/** @addtogroup CMSIS_CM0_SCB CMSIS CM0 SCB
N memory mapped structure for System Control Block (SCB)
N @{
N */
Ntypedef struct
N{
N __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */
X volatile const uint32_t CPUID;
N __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */
X volatile uint32_t ICSR;
N uint32_t RESERVED0;
N __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */
X volatile uint32_t AIRCR;
N __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */
X volatile uint32_t SCR;
N __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */
X volatile uint32_t CCR;
N uint32_t RESERVED1;
N __IO uint32_t SHP[2]; /*!< Offset: 0x1C System Handlers Priority Registers. [0] is RESERVED */
X volatile uint32_t SHP[2];
N __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */
X volatile uint32_t SHCSR;
N uint32_t RESERVED2[2];
N __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */
X volatile uint32_t DFSR;
N} SCB_Type;
N
N/* SCB CPUID Register Definitions */
N#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
N#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
N
N#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
N#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
N
N#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
N#define SCB_CPUID_ARCHITECTURE_Msk (0xFul << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
N
N#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
N#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
N
N#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
N#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
N
N/* SCB Interrupt Control State Register Definitions */
N#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
N#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
N
N#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
N#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
N
N#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
N#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
N
N#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
N#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
N
N#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
N#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
N
N#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
N#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
N
N#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
N#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
N
N#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
N#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
N
N#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
N#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
N
N/* SCB Application Interrupt and Reset Control Register Definitions */
N#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
N#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
N
N#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
N#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
N
N#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
N#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
N
N#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
N#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
N
N#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
N#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
N
N/* SCB System Control Register Definitions */
N#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
N#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
N
N#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
N#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
N
N#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
N#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
N
N/* SCB Configuration Control Register Definitions */
N#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
N#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
N
N#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
N#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
N
N/* SCB System Handler Control and State Register Definitions */
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