lcd1602.lst

cortex-m0 LCD1602程序

L 1 "..\Source\LCD1602.c"
N/*********************淘宝：http://quanmao.taobao.com **************************
N程序名： 　　 LCD1602.C
N编写人： 　　 李全茂　
N编写时间：　　2010年7月15日
N硬件支持：　　WJ-4.0开发板，单片机M0516,通过跳线连接
N接口说明：　　
N修改日志：　　
N　　NO.1-     移植到新塘的M0516上
N*******************************************************************************
N说明：
N*****************技术论坛：http://www.wang1jin.com/bbs*************************/
N#include "LCD1602.H"
L 1 "..\Source\LCD1602.H" 1
N/*********************淘宝：http://quanmao.taobao.com **************************
N程序名： 　　 LCD1602.h
N编写人： 　　 李全茂　
N编写时间：　　2010年7月15日
N硬件支持：　　WJ-4.0开发板，晶振12M 
N接口说明：　　
N修改日志：　　
N　　NO.1-
N*******************************************************************************
N说明：	
N*****************技术论坛：http://www.wang1jin.com/bbs*************************/
N
N#ifndef _LCD1602_H_
N#define _LCD1602_H_
N
N/*******************************************************************************
N// 基本宏定义
N******************************************************************************/
N#define WRITE 0
N#define READ  1
N#define Com_Reg	0
N#define Data_Reg 1 
N
Nextern void LCD1602_Init(void);
Nextern void LCD1602_WriteByte(unsigned char x,unsigned char y,unsigned char Data);
Nextern void LCD1602_WriteString(unsigned char x,unsigned char y,unsigned char *String);
Nextern unsigned char ReadRegister(unsigned char _Register);
N
N#endif
L 13 "..\Source\LCD1602.c" 2
N//#include "M051Series.h"
N#include "NUC1xx.h"
L 1 "..\Lib\CMSIS\CM0\DeviceSupport\Nuvoton\NUC1xx\NUC1xx.h" 1
N/*---------------------------------------------------------------------------------------------------------*/
N/*                                                                                                         */
N/* Copyright (c) Nuvoton Technology Corp. All rights reserved.                                             */
N/*                                                                                                         */
N/*---------------------------------------------------------------------------------------------------------*/
N
N#ifndef __NUC1xx_H__
N#define __NUC1xx_H__
N
N              
N/*
N * ==========================================================================
N * ---------- Interrupt Number Definition -----------------------------------
N * ==========================================================================
N*/
N 
Ntypedef enum IRQn
N{
N/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/
N  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */
N  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                     */
N  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                       */
N  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                       */
N  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                   */
N
N/************************ NUC1xx Interrupt Numbers ************************************************/
N  BOD_IRQn                  = 0,
N  WDT_IRQn                  = 1,
N  EINT0_IRQn                = 2,
N  EINT1_IRQn                = 3,
N  GPAB_IRQn                 = 4,
N  GPCDE_IRQn                = 5,
N  PWMA_IRQn                 = 6,
N  PWMB_IRQn                 = 7,
N  TMR0_IRQn                 = 8,
N  TMR1_IRQn                 = 9,
N  TMR2_IRQn                 = 10,
N  TMR3_IRQn                 = 11,
N  UART0_IRQn                = 12,
N  UART1_IRQn                = 13,
N  SPI0_IRQn                 = 14,
N  SPI1_IRQn                 = 15,
N  SPI2_IRQn                 = 16,
N  SPI3_IRQn                 = 17,
N  I2C0_IRQn                 = 18,
N  I2C1_IRQn                 = 19,
N  CAN0_IRQn                 = 20,
N  CAN1_IRQn                 = 21,
N  SD_IRQn                   = 22,
N  USBD_IRQn                 = 23,
N  PS2_IRQn                  = 24,
N  ACMP_IRQn                 = 25,
N  PDMA_IRQn                 = 26,
N  I2S_IRQn                  = 27,
N  PWRWU_IRQn                = 28,
N  ADC_IRQn                  = 29,
N  DAC_IRQn                  = 30,
N  RTC_IRQn                  = 31
N} IRQn_Type;
N
N
N/*
N * ==========================================================================
N * ----------- Processor and Core Peripheral Section ------------------------
N * ==========================================================================
N */
N
N/* Configuration of the Cortex-M0 Processor and Core Peripherals */
N#define __MPU_PRESENT           0       /*!< armikcmu does not provide a MPU present or not       */
N#define __NVIC_PRIO_BITS        2       /*!< armikcmu Supports 2 Bits for the Priority Levels     */
N#define __Vendor_SysTickConfig  0       /*!< Set to 1 if different SysTick Config is used         */
N
N
N#include "core_cm0.h"                   /* Cortex-M0 processor and core peripherals               */
L 1 "..\Lib\CMSIS\CM0\CoreSupport\core_cm0.h" 1
N/**************************************************************************//**
N * @file     core_cm0.h
N * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
N * @version  V1.30
N * @date     30. October 2009
N *
N * @note
N * Copyright (C) 2009 ARM Limited. All rights reserved.
N *
N * @par
N * ARM Limited (ARM) is supplying this software for use with Cortex-M 
N * processor based microcontrollers.  This file can be freely distributed 
N * within development tools that are supporting such ARM based processors. 
N *
N * @par
N * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
N * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
N * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
N * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
N * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
N *
N ******************************************************************************/
N
N#ifndef __CM0_CORE_H__
N#define __CM0_CORE_H__
N
N/** @addtogroup CMSIS_CM0_core_LintCinfiguration CMSIS CM0 Core Lint Configuration
N *
N * List of Lint messages which will be suppressed and not shown:
N *   - not yet checked
N * .
N * Note:  To re-enable a Message, insert a space before 'lint' *
N *
N */
N
N
N/** @addtogroup CMSIS_CM0_core_definitions CM0 Core Definitions
N  This file defines all structures and symbols for CMSIS core:
N    - CMSIS version number
N    - Cortex-M core registers and bitfields
N    - Cortex-M core peripheral base address
N  @{
N */
N
N#ifdef __cplusplus
S extern "C" {
N#endif 
N
N#define __CM0_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */
N#define __CM0_CMSIS_VERSION_SUB   (0x30)                                                       /*!< [15:0]  CMSIS HAL sub version  */
N#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
N
N#define __CORTEX_M                (0x00)                                                       /*!< Cortex core                    */
N
N#include <stdint.h>                           /* Include standard types */
L 1 "C:\Keil\ARM\RV31\INC\stdint.h" 1
N/* Copyright (C) ARM Ltd., 1999 */
N/* All rights reserved */
N
N/*
N * RCS $Revision: 137748 $
N * Checkin $Date: 2008-09-11 17:34:24 +0100 (Thu, 11 Sep 2008) $
N * Revising $Author: agrant $
N */
N
N#ifndef __stdint_h
N#define __stdint_h
N
N  #ifndef __STDINT_DECLS
N  #define __STDINT_DECLS
N
N    #undef __CLIBNS
N
N    #ifdef __cplusplus
S      namespace std {
S          #define __CLIBNS std::
S          extern "C" {
N    #else
N      #define __CLIBNS
N    #endif  /* __cplusplus */
N
N
N/*
N * 'signed' is redundant below, except for 'signed char' and if
N * the typedef is used to declare a bitfield.
N * '__int64' is used instead of 'long long' so that this header
N * can be used in --strict mode.
N */
N
N    /* 7.18.1.1 */
N
N    /* exact-width signed integer types */
Ntypedef   signed          char int8_t;
Ntypedef   signed short     int int16_t;
Ntypedef   signed           int int32_t;
Ntypedef   signed       __int64 int64_t;
N
N    /* exact-width unsigned integer types */
Ntypedef unsigned          char uint8_t;
Ntypedef unsigned short     int uint16_t;
Ntypedef unsigned           int uint32_t;
Ntypedef unsigned       __int64 uint64_t;
N
N    /* 7.18.1.2 */
N
N    /* smallest type of at least n bits */
N    /* minimum-width signed integer types */
Ntypedef   signed          char int_least8_t;
Ntypedef   signed short     int int_least16_t;
Ntypedef   signed           int int_least32_t;
Ntypedef   signed       __int64 int_least64_t;
N
N    /* minimum-width unsigned integer types */
Ntypedef unsigned          char uint_least8_t;
Ntypedef unsigned short     int uint_least16_t;
Ntypedef unsigned           int uint_least32_t;
Ntypedef unsigned       __int64 uint_least64_t;
N
N    /* 7.18.1.3 */
N
N    /* fastest minimum-width signed integer types */
Ntypedef   signed           int int_fast8_t;
Ntypedef   signed           int int_fast16_t;
Ntypedef   signed           int int_fast32_t;
Ntypedef   signed       __int64 int_fast64_t;
N
N    /* fastest minimum-width unsigned integer types */
Ntypedef unsigned           int uint_fast8_t;
Ntypedef unsigned           int uint_fast16_t;
Ntypedef unsigned           int uint_fast32_t;
Ntypedef unsigned       __int64 uint_fast64_t;
N
N    /* 7.18.1.4 integer types capable of holding object pointers */
Ntypedef   signed           int intptr_t;
Ntypedef unsigned           int uintptr_t;
N
N    /* 7.18.1.5 greatest-width integer types */
Ntypedef   signed       __int64 intmax_t;
Ntypedef unsigned       __int64 uintmax_t;
N
N
N#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS)
X#if !0L || 0L
N
N    /* 7.18.2.1 */
N
N    /* minimum values of exact-width signed integer types */
N#define INT8_MIN                   -128
N#define INT16_MIN                -32768
N#define INT32_MIN          (~0x7fffffff)   /* -2147483648 is unsigned */
N#define INT64_MIN  __ESCAPE__(~0x7fffffffffffffffll) /* -9223372036854775808 is unsigned */
N
N    /* maximum values of exact-width signed integer types */
N#define INT8_MAX                    127
N#define INT16_MAX                 32767
N#define INT32_MAX            2147483647
N#define INT64_MAX  __ESCAPE__(9223372036854775807ll)
N
N    /* maximum values of exact-width unsigned integer types */
N#define UINT8_MAX                   255
N#define UINT16_MAX                65535
N#define UINT32_MAX           4294967295u
N#define UINT64_MAX __ESCAPE__(18446744073709551615ull)
N
N    /* 7.18.2.2 */
N
N    /* minimum values of minimum-width signed integer types */
N#define INT_LEAST8_MIN                   -128
N#define INT_LEAST16_MIN                -32768
N#define INT_LEAST32_MIN          (~0x7fffffff)
N#define INT_LEAST64_MIN  __ESCAPE__(~0x7fffffffffffffffll)
N
N    /* maximum values of minimum-width signed integer types */
N#define INT_LEAST8_MAX                    127
N#define INT_LEAST16_MAX                 32767
N#define INT_LEAST32_MAX            2147483647
N#define INT_LEAST64_MAX  __ESCAPE__(9223372036854775807ll)
N
N    /* maximum values of minimum-width unsigned integer types */
N#define UINT_LEAST8_MAX                   255