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N
N
N/** @addtogroup CMSIS_CM0_SysTick CMSIS CM0 SysTick
N memory mapped structure for SysTick
N @{
N */
Ntypedef struct
N{
N __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
X volatile uint32_t CTRL;
N __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
X volatile uint32_t LOAD;
N __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
X volatile uint32_t VAL;
N __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
X volatile const uint32_t CALIB;
N} SysTick_Type;
N
N/* SysTick Control / Status Register Definitions */
N#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
N#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
N
N#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
N#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
N
N#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
N#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
N
N#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
N#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
N
N/* SysTick Reload Register Definitions */
N#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
N#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
N
N/* SysTick Current Register Definitions */
N#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
N#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
N
N/* SysTick Calibration Register Definitions */
N#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
N#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
N
N#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
N#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
N
N#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
N#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
N/*@}*/ /* end of group CMSIS_CM0_SysTick */
N
N
N/** @addtogroup CMSIS_CM0_CoreDebug CMSIS CM0 Core Debug
N memory mapped structure for Core Debug Register
N @{
N */
Ntypedef struct
N{
N __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */
X volatile uint32_t DHCSR;
N __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */
X volatile uint32_t DCRSR;
N __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */
X volatile uint32_t DCRDR;
N __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */
X volatile uint32_t DEMCR;
N} CoreDebug_Type;
N
N/* Debug Halting Control and Status Register */
N#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
N#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
N
N#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
N#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
N
N#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
N#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
N
N#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
N#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
N
N#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
N#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
N
N#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
N#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
N
N#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
N#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
N
N#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
N#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
N
N#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
N#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
N
N#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
N#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
N
N#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
N#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
N
N/* Debug Core Register Selector Register */
N#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
N#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
N
N#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
N#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
N
N/* Debug Exception and Monitor Control Register */
N#define CoreDebug_DEMCR_DWTENA_Pos 24 /*!< CoreDebug DEMCR: DWTENA Position */
N#define CoreDebug_DEMCR_DWTENA_Msk (1ul << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
N
N#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
N#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
N
N#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
N#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
N/*@}*/ /* end of group CMSIS_CM0_CoreDebug */
N
N
N/* Memory mapping of Cortex-M0 Hardware */
N#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
N#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
N#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
N#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
N#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
N
N#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
N#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
N#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
N#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
N
N/*@}*/ /* end of group CMSIS_CM0_core_register */
N
N
N/*******************************************************************************
N * Hardware Abstraction Layer
N ******************************************************************************/
N
N#if defined ( __CC_ARM )
X#if 1L
N #define __ASM __asm /*!< asm keyword for ARM Compiler */
N #define __INLINE __inline /*!< inline keyword for ARM Compiler */
N
N#elif defined ( __ICCARM__ )
S #define __ASM __asm /*!< asm keyword for IAR Compiler */
S #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
S
S#elif defined ( __GNUC__ )
S #define __ASM __asm /*!< asm keyword for GNU Compiler */
S #define __INLINE inline /*!< inline keyword for GNU Compiler */
S
S#elif defined ( __TASKING__ )
S #define __ASM __asm /*!< asm keyword for TASKING Compiler */
S #define __INLINE inline /*!< inline keyword for TASKING Compiler */
S
N#endif
N
N
N/* ################### Compiler specific Intrinsics ########################### */
N
N#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
X#if 1L
N/* ARM armcc specific functions */
N
N#define __enable_fault_irq __enable_fiq
N#define __disable_fault_irq __disable_fiq
N
N#define __NOP __nop
N#define __WFI __wfi
N#define __WFE __wfe
N#define __SEV __sev
N#define __ISB() __isb(0)
N#define __DSB() __dsb(0)
N#define __DMB() __dmb(0)
N#define __REV __rev
N
N
N/* intrinsic void __enable_irq(); */
N/* intrinsic void __disable_irq(); */
N
N
N/**
N * @brief Return the Process Stack Pointer
N *
N * @return ProcessStackPointer
N *
N * Return the actual process stack pointer
N */
Nextern uint32_t __get_PSP(void);
N
N/**
N * @brief Set the Process Stack Pointer
N *
N * @param topOfProcStack Process Stack Pointer
N *
N * Assign the value ProcessStackPointer to the MSP
N * (process stack pointer) Cortex processor register
N */
Nextern void __set_PSP(uint32_t topOfProcStack);
N
N/**
N * @brief Return the Main Stack Pointer
N *
N * @return Main Stack Pointer
N *
N * Return the current value of the MSP (main stack pointer)
N * Cortex processor register
N */
Nextern uint32_t __get_MSP(void);
N
N/**
N * @brief Set the Main Stack Pointer
N *
N * @param topOfMainStack Main Stack Pointer
N *
N * Assign the value mainStackPointer to the MSP
N * (main stack pointer) Cortex processor register
N */
Nextern void __set_MSP(uint32_t topOfMainStack);
N
N/**
N * @brief Reverse byte order in unsigned short value
N *
N * @param value value to reverse
N * @return reversed value
N *
N * Reverse byte order in unsigned short value
N */
Nextern uint32_t __REV16(uint16_t value);
N
N/**
N * @brief Reverse byte order in signed short value with sign extension to integer
N *
N * @param value value to reverse
N * @return reversed value
N *
N * Reverse byte order in signed short value with sign extension to integer
N */
Nextern int32_t __REVSH(int16_t value);
N
N
N#if (__ARMCC_VERSION < 400000)
X#if (410713 < 400000)
S
S/**
S * @brief Return the Priority Mask value
S *
S * @return PriMask
S *
S * Return state of the priority mask bit from the priority mask register
S */
Sextern uint32_t __get_PRIMASK(void);
S
S/**
S * @brief Set the Priority Mask value
S *
S * @param priMask PriMask
S *
S * Set the priority mask bit in the priority mask register
S */
Sextern void __set_PRIMASK(uint32_t priMask);
S
S/**
S * @brief Return the Control Register value
S *
S * @return Control value
S *
S * Return the content of the control register
S */
Sextern uint32_t __get_CONTROL(void);
S
S/**
S * @brief Set the Control Register value
S *
S * @param control Control value
S *
S * Set the control register
S */
Sextern void __set_CONTROL(uint32_t control);
S
N#else /* (__ARMCC_VERSION >= 400000) */
N
N
N/**
N * @brief Return the Priority Mask value
N *
N * @return PriMask
N *
N * Return state of the priority mask bit from the priority mask register
N */
Nstatic __INLINE uint32_t __get_PRIMASK(void)
Xstatic __inline uint32_t __get_PRIMASK(void)
N{
N register uint32_t __regPriMask __ASM("primask");
X register uint32_t __regPriMask __asm("primask");
N return(__regPriMask);
N}
N
N/**
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