📄 system_nuc1xx.lst
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N SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
N PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
N SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
N
N/************************ NUC1xx Interrupt Numbers ************************************************/
N BOD_IRQn = 0,
N WDT_IRQn = 1,
N EINT0_IRQn = 2,
N EINT1_IRQn = 3,
N GPAB_IRQn = 4,
N GPCDE_IRQn = 5,
N PWMA_IRQn = 6,
N PWMB_IRQn = 7,
N TMR0_IRQn = 8,
N TMR1_IRQn = 9,
N TMR2_IRQn = 10,
N TMR3_IRQn = 11,
N UART0_IRQn = 12,
N UART1_IRQn = 13,
N SPI0_IRQn = 14,
N SPI1_IRQn = 15,
N SPI2_IRQn = 16,
N SPI3_IRQn = 17,
N I2C0_IRQn = 18,
N I2C1_IRQn = 19,
N CAN0_IRQn = 20,
N CAN1_IRQn = 21,
N SD_IRQn = 22,
N USBD_IRQn = 23,
N PS2_IRQn = 24,
N ACMP_IRQn = 25,
N PDMA_IRQn = 26,
N I2S_IRQn = 27,
N PWRWU_IRQn = 28,
N ADC_IRQn = 29,
N DAC_IRQn = 30,
N RTC_IRQn = 31
N} IRQn_Type;
N
N
N/*
N * ==========================================================================
N * ----------- Processor and Core Peripheral Section ------------------------
N * ==========================================================================
N */
N
N/* Configuration of the Cortex-M0 Processor and Core Peripherals */
N#define __MPU_PRESENT 0 /*!< armikcmu does not provide a MPU present or not */
N#define __NVIC_PRIO_BITS 2 /*!< armikcmu Supports 2 Bits for the Priority Levels */
N#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
N
N
N#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
L 1 "..\Lib\CMSIS\CM0\CoreSupport\core_cm0.h" 1
N/**************************************************************************//**
N * @file core_cm0.h
N * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
N * @version V1.30
N * @date 30. October 2009
N *
N * @note
N * Copyright (C) 2009 ARM Limited. All rights reserved.
N *
N * @par
N * ARM Limited (ARM) is supplying this software for use with Cortex-M
N * processor based microcontrollers. This file can be freely distributed
N * within development tools that are supporting such ARM based processors.
N *
N * @par
N * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
N * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
N * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
N * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
N * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
N *
N ******************************************************************************/
N
N#ifndef __CM0_CORE_H__
N#define __CM0_CORE_H__
N
N/** @addtogroup CMSIS_CM0_core_LintCinfiguration CMSIS CM0 Core Lint Configuration
N *
N * List of Lint messages which will be suppressed and not shown:
N * - not yet checked
N * .
N * Note: To re-enable a Message, insert a space before 'lint' *
N *
N */
N
N
N/** @addtogroup CMSIS_CM0_core_definitions CM0 Core Definitions
N This file defines all structures and symbols for CMSIS core:
N - CMSIS version number
N - Cortex-M core registers and bitfields
N - Cortex-M core peripheral base address
N @{
N */
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N#define __CM0_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
N#define __CM0_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
N#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
N
N#define __CORTEX_M (0x00) /*!< Cortex core */
N
N#include <stdint.h> /* Include standard types */
N
N#if defined (__ICCARM__)
X#if 0L
S #include <intrinsics.h> /* IAR Intrinsics */
N#endif
N
N
N#ifndef __NVIC_PRIO_BITS
S #define __NVIC_PRIO_BITS 2 /*!< standard definition for NVIC Priority Bits */
N#endif
N
N
N
N
N/**
N * IO definitions
N *
N * define access restrictions to peripheral registers
N */
N
N#ifdef __cplusplus
S #define __I volatile /*!< defines 'read only' permissions */
N#else
N #define __I volatile const /*!< defines 'read only' permissions */
N#endif
N#define __O volatile /*!< defines 'write only' permissions */
N#define __IO volatile /*!< defines 'read / write' permissions */
N
N
N
N/*******************************************************************************
N * Register Abstraction
N ******************************************************************************/
N/** @addtogroup CMSIS_CM0_core_register CMSIS CM0 Core Register
N @{
N*/
N
N
N/** @addtogroup CMSIS_CM0_NVIC CMSIS CM0 NVIC
N memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
N @{
N */
Ntypedef struct
N{
N __IO uint32_t ISER[1]; /*!< (Offset: 0x000) Interrupt Set Enable Register */
X volatile uint32_t ISER[1];
N uint32_t RESERVED0[31];
N __IO uint32_t ICER[1]; /*!< (Offset: 0x080) Interrupt Clear Enable Register */
X volatile uint32_t ICER[1];
N uint32_t RSERVED1[31];
N __IO uint32_t ISPR[1]; /*!< (Offset: 0x100) Interrupt Set Pending Register */
X volatile uint32_t ISPR[1];
N uint32_t RESERVED2[31];
N __IO uint32_t ICPR[1]; /*!< (Offset: 0x180) Interrupt Clear Pending Register */
X volatile uint32_t ICPR[1];
N uint32_t RESERVED3[31];
N uint32_t RESERVED4[64];
N __IO uint32_t IPR[8]; /*!< (Offset: 0x3EC) Interrupt Priority Register */
X volatile uint32_t IPR[8];
N} NVIC_Type;
N/*@}*/ /* end of group CMSIS_CM0_NVIC */
N
N
N/** @addtogroup CMSIS_CM0_SCB CMSIS CM0 SCB
N memory mapped structure for System Control Block (SCB)
N @{
N */
Ntypedef struct
N{
N __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */
X volatile const uint32_t CPUID;
N __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */
X volatile uint32_t ICSR;
N uint32_t RESERVED0;
N __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */
X volatile uint32_t AIRCR;
N __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */
X volatile uint32_t SCR;
N __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */
X volatile uint32_t CCR;
N uint32_t RESERVED1;
N __IO uint32_t SHP[2]; /*!< Offset: 0x1C System Handlers Priority Registers. [0] is RESERVED */
X volatile uint32_t SHP[2];
N __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */
X volatile uint32_t SHCSR;
N uint32_t RESERVED2[2];
N __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */
X volatile uint32_t DFSR;
N} SCB_Type;
N
N/* SCB CPUID Register Definitions */
N#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
N#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
N
N#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
N#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
N
N#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
N#define SCB_CPUID_ARCHITECTURE_Msk (0xFul << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
N
N#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
N#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
N
N#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
N#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
N
N/* SCB Interrupt Control State Register Definitions */
N#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
N#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
N
N#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
N#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
N
N#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
N#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
N
N#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
N#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
N
N#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
N#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
N
N#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
N#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
N
N#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
N#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
N
N#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
N#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
N
N#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
N#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
N
N/* SCB Application Interrupt and Reset Control Register Definitions */
N#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
N#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
N
N#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
N#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
N
N#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
N#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
N
N#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
N#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
N
N#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
N#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
N
N/* SCB System Control Register Definitions */
N#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
N#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
N
N#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
N#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
N
N#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
N#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
N
N/* SCB Configuration Control Register Definitions */
N#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
N#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
N
N#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
N#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
N
N/* SCB System Handler Control and State Register Definitions */
N#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
N#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
N
N/* SCB Debug Fault Status Register Definitions */
N#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
N#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
N
N#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
N#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
N
N#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
N#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
N
N#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
N#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
N
N#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
N#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
N/*@}*/ /* end of group CMSIS_CM0_SCB */
N
N
N/** @addtogroup CMSIS_CM0_SysTick CMSIS CM0 SysTick
N memory mapped structure for SysTick
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