📄 startup_nuc1xx.lst
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ARM Macro Assembler Page 1
1 00000000 ;/*-----------------------------------------------------
----------------------------------------------------*/
2 00000000 ;/*
*/
3 00000000 ;/* Copyright(c) 2009 Nuvoton Technology Corp. All right
s reserved. */
4 00000000 ;/*
*/
5 00000000 ;/*-----------------------------------------------------
----------------------------------------------------*/
6 00000000
7 00000000 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8 00000000
9 00000000 GBLL SEMIHOSTED
10 00000000 FALSE
SEMIHOSTED
SETL {FALSE}
11 00000000
12 00000000
13 00000000 50000200
CLK_BA_base
EQU 0x50000200
14 00000000 00000000
PWRCON EQU 0x00
15 00000000 00000004
AHBCLK EQU 0x04
16 00000000 00000008
APBCLK EQU 0x08
17 00000000 00000010
CLKSEL0 EQU 0x10
18 00000000 00000014
CLKSEL1 EQU 0x14
19 00000000 00000018
CLKDIV EQU 0x18
20 00000000 00000020
PLLCON EQU 0x20
21 00000000 00000030
TEST_S EQU 0x30
22 00000000
23 00000000 50000208
CLK_BA_APBCLK
EQU 0x50000208
24 00000000
25 00000000 ;// Define clock enable registers
26 00000000
27 00000000 50000208
ADC_COMP_CLK
EQU 0x50000208
28 00000000 10000000
ADC_enable
EQU 0x10000000
29 00000000 40000000
COMP_enable
EQU 0x40000000
30 00000000
31 00000000 50000204
PDMA_CLK
EQU 0x50000204
32 00000000 00000003
ARM Macro Assembler Page 2
PDMA_enable
EQU 0x00000003
33 00000000
34 00000000 ;; bit 0 CPU_EN
35 00000000 ;; bit 1 PDMA_EN
36 00000000
37 00000000
38 00000000
39 00000000
40 00000000 ;// Define COMP registers base
41 00000000 400D0000
COMP_base
EQU 0x400D0000
42 00000000 00000000
CMP1CR EQU 0x00
43 00000000 00000004
CMP2CR EQU 0x04
44 00000000 00000008
CMPSR EQU 0x08
45 00000000
46 00000000 ;// Define ADC registers base
47 00000000 400E0000
ADC_base
EQU 0x400E0000
48 00000000 00000000
ADDR0 EQU 0x00
49 00000000 00000004
ADDR1 EQU 0x04
50 00000000 00000008
ADDR2 EQU 0x08
51 00000000 0000000C
ADDR3 EQU 0x0c
52 00000000 00000010
ADDR4 EQU 0x10
53 00000000 00000014
ADDR5 EQU 0x14
54 00000000 00000018
ADDR6 EQU 0x18
55 00000000 0000001C
ADDR7 EQU 0x1c
56 00000000 00000020
ADCR EQU 0x20
57 00000000 00000024
ADCHER EQU 0x24
58 00000000 00000028
ADCMPR0 EQU 0x28
59 00000000 0000002C
ADCMPR1 EQU 0x2c
60 00000000 00000030
ADSR EQU 0x30
61 00000000 00000034
ADCALR EQU 0x34
62 00000000 00000038
ADCFCR EQU 0x38
63 00000000 0000003C
ADCALD EQU 0x3c
64 00000000
65 00000000 ;// Pattern Table
66 00000000 55555555
ARM Macro Assembler Page 3
pattern_55555555
EQU 0x55555555
67 00000000 AAAAAAAA
pattern_aaaaaaaa
EQU 0xaaaaaaaa
68 00000000 00005555
pattern_00005555
EQU 0x00005555
69 00000000 0000AAAA
pattern_0000aaaa
EQU 0x0000aaaa
70 00000000 05550515
pattern_05550515
EQU 0x05550515
71 00000000 0AAA0A2A
pattern_0aaa0a2a
EQU 0x0aaa0a2a
72 00000000
73 00000000 ;// Define PDMA regsiter base
74 00000000 50008000
PDMA_BA_ch0_base
EQU 0x50008000
75 00000000 50008100
PDMA_BA_ch1_base
EQU 0x50008100
76 00000000 50008200
PDMA_BA_ch2_base
EQU 0x50008200
77 00000000 50008300
PDMA_BA_ch3_base
EQU 0x50008300
78 00000000 50008400
PDMA_BA_ch4_base
EQU 0x50008400
79 00000000 50008500
PDMA_BA_ch5_base
EQU 0x50008500
80 00000000 50008600
PDMA_BA_ch6_base
EQU 0x50008600
81 00000000 50008700
PDMA_BA_ch7_base
EQU 0x50008700
82 00000000
83 00000000 50008F00
PDMA_BA_GCR
EQU 0x50008F00
84 00000000 50008F00
PDMA_BA_GCR_base
EQU 0x50008F00
85 00000000
86 00000000 00000000
PDMA_GCRCSR
EQU 0X00
87 00000000 00000004
PDMA_PDSSR2
EQU 0X04
88 00000000 00000008
PDMA_PDSSR1
ARM Macro Assembler Page 4
EQU 0X08 ;; PDMA channel sel
ect 0x77000000
89 00000000 0000000C
PDMA_GCRISR
EQU 0X0C
90 00000000
91 00000000 0000FF00
PDMA_GLOBAL_enable
EQU 0x0000FF00
92 00000000
93 00000000
94 00000000 00000000
PDMA_CSR
EQU 0X00
95 00000000 00000004
PDMA_SAR
EQU 0X04
96 00000000 00000008
PDMA_DAR
EQU 0X08
97 00000000 0000000C
PDMA_BCR
EQU 0X0C
98 00000000 00000014
PDMA_CSAR
EQU 0X14
99 00000000 00000018
PDMA_CDAR
EQU 0X18
100 00000000 0000001C
PDMA_CBSR
EQU 0X1C
101 00000000 00000020
PDMA_IER
EQU 0X20
102 00000000 00000024
PDMA_ISR
EQU 0X24
103 00000000 00000028
PDMA_CTCSR
EQU 0X28
104 00000000 0000002C
PDMA_SASOCR
EQU 0X2C
105 00000000 00000030
PDMA_DASOCR
EQU 0X30
106 00000000 00000080
PDMA_SBUF0
EQU 0X80
107 00000000 00000084
PDMA_SBUF1
EQU 0X84
108 00000000 00000088
PDMA_SBUF2
EQU 0X88
109 00000000 0000008C
PDMA_SBUF3
EQU 0X8C
ARM Macro Assembler Page 5
110 00000000
111 00000000
112 00000000 ;// Define VIC control register
113 00000000 FFFF0000
VIC_base
EQU 0xFFFF0000
114 00000000 0000003C
VIC_SCR15
EQU 0x003c
115 00000000 000000BC
VIC_SVR15
EQU 0x00bc
116 00000000 00000040
VIC_SCR16
EQU 0x0040
117 00000000 000000C0
VIC_SVR16
EQU 0x00c0
118 00000000 00000078
VIC_SCR30
EQU 0x0078
119 00000000 000000F8
VIC_SVR30
EQU 0x00f8
120 00000000 00000318
VIC_MECR
EQU 0x0318
121 00000000 0000031C
VIC_MDCR
EQU 0x031c
122 00000000 00000130
VIC_EOSCR
EQU 0x0130
123 00000000
124 00000000 ;//==================================
125 00000000 50000300
INT_BA_base
EQU 0x50000300
126 00000000
127 00000000
128 00000000 ;// Parameter table
129 00000000 00002980
ADC_PDMA_CFG
EQU 0x00002980
130 00000000 C0000000
ADC_PDMA_DST
EQU 0xC0000000
131 00000000 E0024200
ADC_PDMA_SRC
EQU 0xE0024200
132 00000000 00030008
ADC_PDMA_TCBL
EQU 0x00030008
133 00000000
134 00000000 ;//==================================
135 00000000
136 00000000
137 00000000 50004000
GPIO_base
ARM Macro Assembler Page 6
EQU 0x50004000
138 00000000 00000040
GPIOB_PMD
EQU 0x0040
139 00000000 00000044
GPIOB_OFFD
EQU 0x0044
140 00000000 00000048
GPIOB_DOUT
EQU 0x0048
141 00000000 0000004C
GPIOB_DMASK
EQU 0x004C
142 00000000 00000050
GPIOB_PIN
EQU 0x0050
143 00000000 00000054
GPIOB_DBEN
EQU 0x0054
144 00000000 00000058
GPIOB_IMD
EQU 0x0058
145 00000000 0000005C
GPIOB_IEN
EQU 0x005C
146 00000000 00000060
GPIOB_ISRC
EQU 0x0060
147 00000000
148 00000000 ;//==================================
149 00000000
150 00000000
151 00000000 50000000
GCR_base
EQU 0x50000000
152 00000000 00000034
GPB_MFP EQU 0x0034
153 00000000
154 00000000
155 00000000
156 00000000
157 00000000
158 00000000 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
159 00000000
160 00000000
161 00000000
162 00000000
163 00000000
164 00000000
165 00000000
166 00000000 00000400
Stack_Size
EQU 0x00000400
167 00000000
168 00000000 AREA STACK, NOINIT, READWRITE, ALIGN
=3
169 00000000 Stack_Mem
SPACE Stack_Size
170 00000400 __initial_sp
ARM Macro Assembler Page 7
171 00000400
172 00000400
173 00000400 ; <h> Heap Configuration
174 00000400 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
175 00000400 ; </h>
176 00000400
177 00000400 00000000
Heap_Size
EQU 0x00000000
178 00000400
179 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN=
3
180 00000000 __heap_base
181 00000000 Heap_Mem
SPACE Heap_Size
182 00000000 __heap_limit
183 00000000
184 00000000
185 00000000 PRESERVE8
186 00000000 THUMB
187 00000000
188 00000000
189 00000000 ; Vector Table Mapped to Address 0 at Reset
190 00000000 AREA RESET, DATA, READONLY
191 00000000 EXPORT __Vectors
192 00000000
193 00000000 00000000
__Vectors
DCD __initial_sp ; Top of Stack
194 00000004 00000000 DCD Reset_Handler ; Reset Handler
195 00000008 00000000 DCD NMI_Handler ; NMI Handler
196 0000000C 00000000 DCD HardFault_Handler ; Hard Fault
Handler
197 00000010 00000000 DCD 0 ; Reserved
198 00000014 00000000 DCD 0 ; Reserved
199 00000018 00000000 DCD 0 ; Reserved
200 0000001C 00000000 DCD 0 ; Reserved
201 00000020 00000000 DCD 0 ; Reserved
202 00000024 00000000 DCD 0 ; Reserved
203 00000028 00000000 DCD 0 ; Reserved
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