📄 drvpwm.c
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(u8IntType == DRVPWM_CAP_RISING_FLAG)? (outp32(&PWMB->CCR0, inp32(&PWMB->CCR0) & (CCR_MASK | BIT6))) : (outp32(&PWMB->CCR0, inp32(&PWMB->CCR0) & (CCR_MASK | BIT7)));
break;
case DRVPWM_CAP5:
(u8IntType == DRVPWM_CAP_RISING_FLAG)? (outp32(&PWMB->CCR0, inp32(&PWMB->CCR0) & (CCR_MASK | BIT22))) : (outp32(&PWMB->CCR0, inp32(&PWMB->CCR0) & (CCR_MASK | BIT23)));
break;
case DRVPWM_CAP6:
(u8IntType == DRVPWM_CAP_RISING_FLAG)? (outp32(&PWMB->CCR2, inp32(&PWMB->CCR2) & (CCR_MASK | BIT6))) : (outp32(&PWMB->CCR2, inp32(&PWMB->CCR2) & (CCR_MASK | BIT7)));
break;
case DRVPWM_CAP7:
(u8IntType == DRVPWM_CAP_RISING_FLAG)? (outp32(&PWMB->CCR2, inp32(&PWMB->CCR2) & (CCR_MASK | BIT22))) : (outp32(&PWMB->CCR2, inp32(&PWMB->CCR2) & (CCR_MASK | BIT23)));
break;
}
}
else
{
switch (u8Capture)
{
case DRVPWM_CAP0:
(u8IntType == DRVPWM_CAP_RISING_FLAG)? (outp32(&PWMA->CCR0, (inp32(&PWMA->CCR0) & ~(BIT4 | BIT20)) & ~BIT6)) : (outp32(&PWMA->CCR0, (inp32(&PWMA->CCR0) & ~(BIT4 | BIT20)) & ~BIT7));
break;
case DRVPWM_CAP1:
(u8IntType == DRVPWM_CAP_RISING_FLAG)? (outp32(&PWMA->CCR0, (inp32(&PWMA->CCR0) & ~(BIT4 | BIT20)) & ~BIT22)) : (outp32(&PWMA->CCR0, (inp32(&PWMA->CCR0) & ~(BIT4 | BIT20)) & ~BIT23));
break;
case DRVPWM_CAP2:
(u8IntType == DRVPWM_CAP_RISING_FLAG)? (outp32(&PWMA->CCR2, (inp32(&PWMA->CCR2) & ~(BIT4 | BIT20)) & ~BIT6)) : (outp32(&PWMA->CCR2, (inp32(&PWMA->CCR2) & ~(BIT4 | BIT20)) & ~BIT7));
break;
case DRVPWM_CAP3:
(u8IntType == DRVPWM_CAP_RISING_FLAG)? (outp32(&PWMA->CCR2, (inp32(&PWMA->CCR2) & ~(BIT4 | BIT20)) & ~BIT22)) : (outp32(&PWMA->CCR2, (inp32(&PWMA->CCR2) & ~(BIT4 | BIT20)) & ~BIT23));
break;
case DRVPWM_CAP4:
(u8IntType == DRVPWM_CAP_RISING_FLAG)? (outp32(&PWMB->CCR0, (inp32(&PWMB->CCR0) & ~(BIT4 | BIT20)) & ~BIT6)) : (outp32(&PWMB->CCR0, (inp32(&PWMB->CCR0) & ~(BIT4 | BIT20)) & ~BIT7));
break;
case DRVPWM_CAP5:
(u8IntType == DRVPWM_CAP_RISING_FLAG)? (outp32(&PWMB->CCR0, (inp32(&PWMB->CCR0) & ~(BIT4 | BIT20)) & ~BIT22)) : (outp32(&PWMB->CCR0, (inp32(&PWMB->CCR0) & ~(BIT4 | BIT20)) & ~BIT23));
break;
case DRVPWM_CAP6:
(u8IntType == DRVPWM_CAP_RISING_FLAG)? (outp32(&PWMB->CCR2, (inp32(&PWMB->CCR2) & ~(BIT4 | BIT20)) & ~BIT6)) : (outp32(&PWMB->CCR2, (inp32(&PWMB->CCR2) & ~(BIT4 | BIT20)) & ~BIT7));
break;
case DRVPWM_CAP7:
(u8IntType == DRVPWM_CAP_RISING_FLAG)? (outp32(&PWMB->CCR2, (inp32(&PWMB->CCR2) & ~(BIT4 | BIT20)) & ~BIT22)) : (outp32(&PWMB->CCR2, (inp32(&PWMB->CCR2) & ~(BIT4 | BIT20)) & ~BIT23));
break;
}
}
}
/*---------------------------------------------------------------------------------------------------------*/
/* Function: DrvPWM_Open */
/* */
/* Parameters: */
/* None */
/* */
/* Returns: */
/* None */
/* */
/* Description: */
/* Enable PWM engine clock and reset PWM */
/*---------------------------------------------------------------------------------------------------------*/
void DrvPWM_Open(void)
{
outp32(&SYSCLK->APBCLK, inp32(&SYSCLK->APBCLK) | 0x00F00000);
outp32(&SYS->IPRSTC2, inp32(&SYS->IPRSTC2) | 0x00300000);
outp32(&SYS->IPRSTC2, inp32(&SYS->IPRSTC2) & ~0x00300000);
}
/*---------------------------------------------------------------------------------------------------------*/
/* Function: DrvPWM_Close */
/* */
/* Parameters: */
/* None */
/* */
/* Returns: */
/* None */
/* */
/* Description: */
/* Disable PWM engine clock and the Capture Input/PWM Output Enable function */
/*---------------------------------------------------------------------------------------------------------*/
void DrvPWM_Close(void)
{
outp32(&PWMA->POE, 0);
PWMA->CAPENR = 0;
outp32(&PWMB->POE, 0);
PWMB->CAPENR = 0;
NVIC_DisableIRQ(PWMA_IRQn);
NVIC_DisableIRQ(PWMB_IRQn);
outp32(&SYS->IPRSTC2, inp32(&SYS->IPRSTC2) | 0x00300000);
outp32(&SYS->IPRSTC2, inp32(&SYS->IPRSTC2) & ~0x00300000);
outp32(&SYSCLK->APBCLK, inp32(&SYSCLK->APBCLK) & ~0x00F00000);
}
/*---------------------------------------------------------------------------------------------------------*/
/* Function: DrvPWM_EnableDeadZone */
/* */
/* Parameters: */
/* u8Timer - [in] DRVPWM_TIMER0 or DRVPWM_TIMER1 / DRVPWM_TIMER2 or DRVPWM_TIMER3*/
/* DRVPWM_TIMER4 or DRVPWM_TIMER5 / DRVPWM_TIMER6 or DRVPWM_TIMER7*/
/* u8Length - [in] Dead Zone Length : 0~255 */
/* i32EnableDeadZone - [in] Enable DeadZone (1) / Diasble DeadZone (0) */
/* */
/* Returns: */
/* None */
/* */
/* Description: */
/* This function is used to set the dead zone length and enable/disable Dead Zone function */
/*---------------------------------------------------------------------------------------------------------*/
void DrvPWM_EnableDeadZone(uint8_t u8Timer, uint8_t u8Length, int32_t i32EnableDeadZone)
{
switch (u8Timer & 0x07)
{
case DRVPWM_TIMER0:
case DRVPWM_TIMER1:
PWMA->PPR.DZI01 = u8Length;
PWMA->PCR.DZEN01 = i32EnableDeadZone;
break;
case DRVPWM_TIMER2:
case DRVPWM_TIMER3:
PWMA->PPR.DZI23 = u8Length;
PWMA->PCR.DZEN23 = i32EnableDeadZone;
break;
case DRVPWM_TIMER4:
case DRVPWM_TIMER5:
PWMB->PPR.DZI01 = u8Length;
PWMB->PCR.DZEN01 = i32EnableDeadZone;
break;
case DRVPWM_TIMER6:
case DRVPWM_TIMER7:
PWMB->PPR.DZI23 = u8Length;
PWMB->PCR.DZEN23 = i32EnableDeadZone;
break;
}
}
/*---------------------------------------------------------------------------------------------------------*/
/* Function: DrvPWM_Enable */
/* */
/* Parameters: */
/* u8Timer - [in] DRVPWM_TIMER0 / DRVPWM_TIMER1 / DRVPWM_TIMER2 / DRVPWM_TIMER3 */
/* DRVPWM_TIMER4 / DRVPWM_TIMER5 / DRVPWM_TIMER6 / DRVPWM_TIMER7 */
/* DRVPWM_CAP0 / DRVPWM_CAP1 / DRVPWM_CAP2 / DRVPWM_CAP3 */
/* DRVPWM_CAP4 / DRVPWM_CAP5 / DRVPWM_CAP6 / DRVPWM_CAP7 */
/* i32Enable - [in] Enable (1) / Disable (0) */
/* */
/* Returns: */
/* None */
/* */
/* Description: */
/* This function is used to enable/disable PWM0~7 timer/capture function */
/*---------------------------------------------------------------------------------------------------------*/
void DrvPWM_Enable(uint8_t u8Timer, int32_t i32Enable)
{
switch (u8Timer & 0x07)
{
case DRVPWM_TIMER0:
case DRVPWM_TIMER1:
case DRVPWM_TIMER2:
case DRVPWM_TIMER3:
outp32(&PWMA->PCR, (inp32(&PWMA->PCR) & ~(1 << ((u8Timer & 0x07) << 3) )) | (i32Enable?(1 << ((u8Timer & 0x07) << 3) ):0) );
break;
case DRVPWM_TIMER4:
case DRVPWM_TIMER5:
case DRVPWM_TIMER6:
case DRVPWM_TIMER7:
outp32(&PWMB->PCR, (inp32(&PWMB->PCR) & ~(1 << (((u8Timer & 0x07)-DRVPWM_TIMER4)<< 3) )) | (i32Enable?(1 << (((u8Timer & 0x07)-DRVPWM_TIMER4) << 3) ):0) );
break;
}
if (u8Timer & 0x10)
{
switch (u8Timer)
{
case DRVPWM_CAP0:
if (s_i32Option)
outp32(&PWMA->CCR0, (inp32(&PWMA->CCR0) & CCR_MASK) | BIT3);
else
outp32(&PWMA->CCR0, (inp32(&PWMA->CCR0) & ~(BIT4 | BIT20)) | BIT3);
break;
case DRVPWM_CAP1:
if (s_i32Option)
outp32(&PWMA->CCR0, (inp32(&PWMA->CCR0) & CCR_MASK) | BIT19);
else
outp32(&PWMA->CCR0, (inp32(&PWMA->CCR0) & ~(BIT4 | BIT20)) | BIT19);
break;
case DRVPWM_CAP2:
if (s_i32Option)
outp32(&PWMA->CCR2, (inp32(&PWMA->CCR2) & CCR_MASK) | BIT3);
else
outp32(&PWMA->CCR2, (inp32(&PWMA->CCR2) & ~(BIT4 | BIT20)) | BIT3);
break;
case DRVPWM_CAP3:
if (s_i32Option)
outp32(&PWMA->CCR2, (inp32(&PWMA->CCR2) & CCR_MASK) | BIT19);
else
outp32(&PWMA->CCR2, (inp32(&PWMA->CCR2) & ~(BIT4 | BIT20)) | BIT19);
break;
case DRVPWM_CAP4:
if (s_i32Option)
outp32(&PWMB->CCR0, (inp32(&PWMB->CCR0) & CCR_MASK) | BIT3);
else
outp32(&PWMB->CCR0, (inp32(&PWMB->CCR0) & ~(BIT4 | BIT20)) | BIT3);
break;
case DRVPWM_CAP5:
if (s_i32Option)
outp32(&PWMB->CCR0, (inp32(&PWMB->CCR0) & CCR_MASK) | BIT19);
else
outp32(&PWMB->CCR0, (inp32(&PWMB->CCR0) & ~(BIT4 | BIT20)) | BIT19);
break;
case DRVPWM_CAP6:
if (s_i32Option)
outp32(&PWMB->CCR2, (inp32(&PWMB->CCR2) & CCR_MASK) | BIT3);
else
outp32(&PWMB->CCR2, (inp32(&PWMB->CCR2) & ~(BIT4 | BIT20)) | BIT3);
break;
case DRVPWM_CAP7:
if (s_i32Option)
outp32(&PWMB->CCR2, (inp32(&PWMB->CCR2) & CCR_MASK) | BIT19);
else
outp32(&PWMB->CCR2, (inp32(&PWMB->CCR2) & ~(BIT4 | BIT20)) | BIT19);
break;
}
}
}
/*---------------------------------------------------------------------------------------------------------*/
/* Function: DrvPWM_SetTimerClk */
/* */
/* Parameters: */
/* u8Timer DRVPWM_TIMER0/DRVPWM_TIMER1/DRVPWM_TIMER2/DRVPWM_TIMER3 */
/* DRVPWM_TIMER4/DRVPWM_TIMER5/DRVPWM_TIMER6/DRVPWM_TIMER7 */
/* DRVPWM_CAP0/DRVPWM_CAP1/DRVPWM_CAP2/DRVPWM_CAP3 */
/* DRVPWM_CAP4/DRVPWM_CAP5/DRVPWM_CAP6/DRVPWM_CAP7 */
/* S_DRVPWM_TIME_DATA_T *sPt */
/* u32Frequency Frequency (Hz) */
/* u8HighPulseRatio High Pulse Ratio */
/* u8Mode DRVPWM_ONE_SHOT_MODE / DRVPWM_AUTO_RELOAD_MODE */
/* bInverter Inverter Enable (TRUE) / Inverter Disable (FALSE) */
/* u8ClockSelector Clock Selector */
/* DRVPWM_CLOCK_DIV_1/DRVPWM_CLOCK_DIV_2/DRVPWM_CLOCK_DIV_4 */
/* DRVPWM_CLOCK_DIV_8/DRVPWM_CLOCK_DIV_16 */
/* (The parameter takes effect when u8Frequency = 0) */
/* u8PreScale Prescale (1 ~ 255). */
/* The PWM input clock = PWM source clock / (u8PreScale + 1) */
/* Note: If the value is set to 0, the timer will stop. */
/* (The parameter takes effect when u8Frequency = 0) */
/* u32Duty Pulse duty */ ⌨️ 快捷键说明
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