drvsys.c

cortex-m0 LCD1602程序

/* Function: DrvSYS_SetIPClock                                                                             */
/*                                                                                                         */
/* Parameters:                                                                                             */
/*               eIpClk     - [in]  E_SYS_WDT_CLK   / E_SYS_RTC_CLK   / E_SYS_TMR0_CLK  / E_SYS_TMR1_CLK   */
/*                                  E_SYS_TMR2_CLK  / E_SYS_TMR3_CLK  / E_SYS_FDIV_CLK  / E_SYS_I2C0_CLK   */
/*                                  E_SYS_I2C1_CLK  / E_SYS_SPI0_CLK  / E_SYS_SPI1_CLK  / E_SYS_SPI2_CLK   */
/*                                  E_SYS_SPI3_CLK  / E_SYS_UART0_CLK / E_SYS_UART1_CLK / E_SYS_UART2_CLK  */
/*                                  E_SYS_PWM01_CLK / E_SYS_PWM23_CLK / E_SYS_PWM45_CLK / E_SYS_PWM67_CLK  */
/*                                  E_SYS_CAN0_CLK  / E_SYS_USBD_CLK  / E_SYS_ADC_CLK   / E_SYS_I2S_CLK    */
/*                                  E_SYS_ACMP_CLK  / E_SYS_PS2_CLK   / E_SYS_PDMA_CLK  / E_SYS_ISP_CLK    */
/*                                  E_SYS_EBI_CLK                                                          */
/*                                                                                                         */
/*               i32Enable  - [in]  1 : Enable / 0 : Disable                                               */
/* Returns:                                                                                                */
/*               None                                                                                      */
/*                                                                                                         */
/* Description:                                                                                            */
/*               Enable/Disable coresponding IP clock                                                      */
/*                                                                                                         */
/* Note:                                                                                                   */
/*               Please make sure that Register Write-Protection Function has been disabled before using   */
/*               this function to enable/disable WDT clock.                                                */
/*               User can check the status of Register Write-Protection Function                           */
/*               with DrvSYS_IsProtectedRegLocked().                                                       */
/*---------------------------------------------------------------------------------------------------------*/
void DrvSYS_SetIPClock(E_SYS_IP_CLK eIpClk, int32_t i32Enable)
{   
    uint32_t u32Reg;

    if (eIpClk == E_SYS_PDMA_CLK)
    {
        SYSCLK->AHBCLK.PDMA_EN = i32Enable;
    }
    else if (eIpClk == E_SYS_EBI_CLK)
    {
        SYSCLK->AHBCLK.EBI_EN = i32Enable;
    }
    else if (eIpClk == E_SYS_ISP_CLK)
    {
        SYSCLK->AHBCLK.ISP_EN = i32Enable;
    }
    else
    {
        u32Reg = *((__IO uint32_t *) &SYSCLK->APBCLK);
        
        if (i32Enable)
        {
            *((__IO uint32_t *) &SYSCLK->APBCLK) = u32Reg | (1<<eIpClk);
        }
        else
        {
            *((__IO uint32_t *) &SYSCLK->APBCLK) = u32Reg & ~(1<<eIpClk);
        }
    }
}

/*---------------------------------------------------------------------------------------------------------*/
/* Function: DrvSYS_SelectHCLKSource                                                                       */
/*                                                                                                         */
/* Parameters:                                                                                             */
/*           u8ClkSrcSel       - [in]   0: External 12M clock                                              */
/*                                      1: External 32K clock                                              */
/*                                      2: PLL clock                                                       */
/*                                      3: Internal 10K clock                                              */
/*                                      7: Internal 22M clock                                              */
/*                                                                                                         */
/* Returns:                                                                                                */
/*                 0:  Success                                                                             */
/*               < 0:  Incorrect value                                                                     */
/*                                                                                                         */
/* Description:                                                                                            */
/*               This function is used to select HCLK clock source                                         */       
/*                                                                                                         */
/* Note:                                                                                                   */
/*               Please make sure that Register Write-Protection Function has been disabled before using   */
/*               this function to select HCLK clock source.                                                */
/*               User can check the status of Register Write-Protection Function                           */
/*               with DrvSYS_IsProtectedRegLocked().                                                       */
/*---------------------------------------------------------------------------------------------------------*/
int32_t DrvSYS_SelectHCLKSource(uint8_t u8ClkSrcSel)
{
    if ((u8ClkSrcSel > 7) || ((u8ClkSrcSel > 3) && (u8ClkSrcSel < 7)))
    {
        return E_DRVSYS_ERR_ARGUMENT;
    }
    else
    {
        SYSCLK->CLKSEL0.HCLK_S = u8ClkSrcSel;
    }
    
    SystemCoreClockUpdate();
    
    return 0;
}

/*---------------------------------------------------------------------------------------------------------*/
/* Function: DrvSYS_SelectSysTickSource                                                                    */
/*                                                                                                         */
/* Parameters:                                                                                             */
/*           u8ClkSrcSel       - [in]   0: External 12M clock                                              */
/*                                      1: External 32K clock                                              */
/*                                      2: External 12M clock / 2                                          */
/*                                      3: HCLK / 2                                                        */
/*                                      7: Internal 22M clock / 2                                          */
/*                                                                                                         */
/* Returns:                                                                                                */
/*                 0:  Success                                                                             */
/*               < 0:  Incorrect value                                                                     */
/*                                                                                                         */
/* Description:                                                                                            */
/*               This function is used to select system tick clock source                                  */       
/*                                                                                                         */
/* Note:                                                                                                   */
/*               Please make sure that Register Write-Protection Function has been disabled before using   */
/*               this function to select system tick clock source.                                         */
/*               User can check the status of Register Write-Protection Function                           */
/*               with DrvSYS_IsProtectedRegLocked().                                                       */
/*---------------------------------------------------------------------------------------------------------*/
int32_t DrvSYS_SelectSysTickSource(uint8_t u8ClkSrcSel)
{
    if ((u8ClkSrcSel > 7) || ((u8ClkSrcSel > 3) && (u8ClkSrcSel < 7)))
    {
        return E_DRVSYS_ERR_ARGUMENT;
    }
    else
    {
        SYSCLK->CLKSEL0.STCLK_S = u8ClkSrcSel;
    }
    return 0;
}

/*---------------------------------------------------------------------------------------------------------*/
/* Function: DrvSYS_SelectIPClockSource                                                                    */
/*                                                                                                         */
/* Parameters:                                                                                             */
/*              eIpClkSrc    - [in]     E_SYS_WDT_CLKSRC   / E_SYS_ADC_CLKSRC  / E_SYS_TMR0_CLKSRC         */
/*                                      E_SYS_TMR1_CLKSRC  / E_SYS_TMR2_CLKSRC / E_SYS_TMR3_CLKSRC         */
/*                                      E_SYS_UART_CLKSRC  / E_SYS_PWM01_CLKSRC/ E_SYS_PWM23_CLKSRC        */
/*                                      E_SYS_PWM45_CLKSRC / E_SYS_PWM67_CLKSRC/ E_SYS_FRQDIV_CLKSRC       */
/*                                      E_SYS_I2S_CLKSRC                                                   */
/*                                                                                                         */
/*              u8ClkSrcSel - [in]    Corresponding clock source                                           */
/*                                                                                                         */
/*           --------------------------------------------------------------------------------------------  */
/*           |  u8ClkSrcSel  |     0x00     |     0x01     |     0x02     |     0x03     |     0x07     |  */
/*           --------------------------------------------------------------------------------------------  */
/*           |      WDT      |   Reserved   | Ext. 32K (*) |   HCLK/2048  | Internal 10K |      X       |  */
/*           --------------------------------------------------------------------------------------------  */
/*           |      ADC      | External 12M |     PLL      |    HCLK (*)  | Internal 22M |      X       |  */
/*           --------------------------------------------------------------------------------------------  */
/*           |    TMR 0~3    | External 12M | External 32K |     HCLK     |   Reserved   | Internal 22M |  */
/*           --------------------------------------------------------------------------------------------  */
/*           |      UART     | External 12M |     PLL      |   Reserved   | Internal 22M |      X       |  */
/*           --------------------------------------------------------------------------------------------  */
/*           |      PWM      | External 12M | External 32K |     HCLK     | Internal 22M |      X       |  */
/*           --------------------------------------------------------------------------------------------  */
/*           |   Frequency   | External 12M | External 32K |     HCLK     | Internal 22M |      X       |  */
/*           | Divider Output|              |              |              |              |              |  */
/*           --------------------------------------------------------------------------------------------  */
/*           |      I2S      | External 12M |     PLL      |     HCLK     | Internal 22M |      X       |  */
/*           --------------------------------------------------------------------------------------------  */
/*                                                                                                         */
/* Returns:                                                                                                */
/*                 0:  Success                                                                             */
/*               < 0:  Incorrect value                                                                     */
/*                                                                                                         */
/* Description:                                                                                            */
/*               This function is used to select IP clock source                                           */
/*                                                                                                         */
/* Note (*) :    Only NuMicro NUC1x0xxxCx Series (Ex. NUC140VE3CN) support External 32K as clock source    */
/*               of Watch Dog Timer and HCLK as clock source of ADC.                                       */
/*                                                                                                         */
/* Note:                                                                                                   */