nuc1xx.h

来自「cortex-m0 LCD1602程序」· C头文件代码 · 共 2,220 行 · 第 1/5 页
2,220 行
    __IO uint32_t  HR1:4;
    __IO uint32_t  HR10:2;
    __I  uint32_t  RESERVE2:10;
} RTC_TLR_T;

typedef struct
{
    __IO uint32_t  DAY1:4;
    __IO uint32_t  DAY10:2;
    __I  uint32_t  RESERVE0:2;
    __IO uint32_t  MON1:4;
    __IO uint32_t  MON10:1;
    __I  uint32_t  RESERVE1:3;
    __IO uint32_t  YEAR1:4;
    __IO uint32_t  YEAR10:4;
    __I  uint32_t  RESERVE2:8;
} RTC_CLR_T;

typedef struct
{
    __IO uint32_t  HR24_HR12:1;
    __I  uint32_t  RESERVE:31;
} RTC_TSSR_T;

typedef struct
{
    __IO uint32_t  DWR:3;
    __I  uint32_t  RESERVE:29;
} RTC_DWR_T;

typedef RTC_TLR_T   RTC_TAR_T;

typedef RTC_CLR_T   RTC_CAR_T;

typedef struct
{
    __IO uint32_t  LIR:1;
    __I  uint32_t  RESERVE:31;
} RTC_LIR_T;

typedef struct
{
    __IO uint32_t  AIER:1;
    __IO uint32_t  TIER:1;
    __I  uint32_t  RESERVE:30;
} RTC_RIER_T;

typedef struct
{
    __IO uint32_t  AIF:1;
    __IO uint32_t  TIF:1;
    __I  uint32_t  RESERVE:30;
} RTC_RIIR_T;

typedef struct
{
    __IO uint32_t  TTR:3;
    __IO uint32_t  TWKE:1;
    __I  uint32_t  RESERVE:28;
} RTC_TTR_T;

typedef struct
{
    union {
        __IO uint32_t u32INIR;
        __IO uint32_t INIR;
    };

    union {
        __IO uint32_t u32AER;
        struct {
            __IO uint32_t  AER:16;
            __I  uint32_t  ENF:1;
            __I  uint32_t  RESERVE1:15;
        } AER;
    };

    union {
        __IO uint32_t u32FCR;
        struct {
            __IO uint32_t  FRACTION:6;
            __I  uint32_t  RESERVE0:2;
            __IO uint32_t  INTEGER:4;
            __I  uint32_t  RESERVE1:20;
        } FCR;
    };

    union {
        __IO uint32_t u32TLR;
        struct {
            __IO uint32_t  SEC1:4;
            __IO uint32_t  SEC10:3;
            __I  uint32_t  RESERVE0:1;
            __IO uint32_t  MIN1:4;
            __IO uint32_t  MIN10:3;
            __I  uint32_t  RESERVE1:1;
            __IO uint32_t  HR1:4;
            __IO uint32_t  HR10:2;
            __I  uint32_t  RESERVE2:10;
        } TLR;
    };

    union {
        __IO uint32_t u32CLR;
        struct {
            __IO uint32_t  DAY1:4;
            __IO uint32_t  DAY10:2;
            __I  uint32_t  RESERVE0:2;
            __IO uint32_t  MON1:4;
            __IO uint32_t  MON10:1;
            __I  uint32_t  RESERVE1:3;
            __IO uint32_t  YEAR1:4;
            __IO uint32_t  YEAR10:4;
            __I  uint32_t  RESERVE2:8;
        } CLR;
    };

    union {
        __IO uint32_t u32TSSR;
        struct {
            __IO uint32_t  HR24_HR12:1;
            __I  uint32_t  RESERVE:31;
        } TSSR;
    };

    union {
        __IO uint32_t u32DWR;
        struct {
            __IO uint32_t  DWR:3;
            __I  uint32_t  RESERVE:29;
        } DWR;
    };

    union {
        __IO uint32_t u32TAR;
        struct {
            __IO uint32_t  SEC1:4;
            __IO uint32_t  SEC10:3;
            __I  uint32_t  RESERVE0:1;
            __IO uint32_t  MIN1:4;
            __IO uint32_t  MIN10:3;
            __I  uint32_t  RESERVE1:1;
            __IO uint32_t  HR1:4;
            __IO uint32_t  HR10:2;
            __I  uint32_t  RESERVE2:10;
        } TAR;
    };

    union {
        __IO uint32_t u32CAR;
        struct {
            __IO uint32_t  DAY1:4;
            __IO uint32_t  DAY10:2;
            __I  uint32_t  RESERVE0:2;
            __IO uint32_t  MON1:4;
            __IO uint32_t  MON10:1;
            __I  uint32_t  RESERVE1:3;
            __IO uint32_t  YEAR1:4;
            __IO uint32_t  YEAR10:4;
            __I  uint32_t  RESERVE2:8;
        } CAR;
    };

    union {
        __IO uint32_t u32LIR;
        struct {
            __IO uint32_t  LIR:1;
            __I  uint32_t  RESERVE:31;
        } LIR;
    };

    union {
        __IO uint32_t u32RIER;
        struct {
            __IO uint32_t  AIER:1;
            __IO uint32_t  TIER:1;
            __I  uint32_t  RESERVE:30;
        } RIER;
    };

    union {
        __IO uint32_t u32RIIR;
        struct {
            __IO uint32_t  AIF:1;
            __IO uint32_t  TIF:1;
            __I  uint32_t  RESERVE:30;
        } RIIR;
    };

    union {
        __IO uint32_t u32TTR;
        struct {
            __IO uint32_t  TTR:3;
            __IO uint32_t  TWKE:1;
            __I  uint32_t  RESERVE:28;
        } TTR;
    };
} RTC_T;

/* RTC INIR Bit Field Definitions */
#define RTC_INIR_INIR_Pos       0  
#define RTC_INIR_INIR_Msk       (0xFFFFFFFFul << RTC_INIR_INIR_Pos)

#define RTC_INIR_ACTIVE_Pos     0  
#define RTC_INIR_ACTIVE_Msk     (1ul << RTC_INIR_ACTIVE_Pos)

/* RTC AER Bit Field Definitions */
#define RTC_AER_ENF_Pos         16  
#define RTC_AER_ENF_Msk         (1ul << RTC_AER_ENF_Pos)

#define RTC_AER_AER_Pos         0  
#define RTC_AER_AER_Msk         (0xFFFFul << RTC_AER_AER_Pos)

/* RTC FCR Bit Field Definitions */
#define RTC_FCR_INTEGER_Pos     8  
#define RTC_FCR_INTEGER_Msk     (0xFul << RTC_FCR_INTEGER_Pos)

#define RTC_FCR_FRACTION_Pos    0  
#define RTC_FCR_FRACTION_Msk    (0x3Ful << RTC_FCR_FRACTION_Pos)

/* RTC TLR Bit Field Definitions */
#define RTC_TLR_10HR_Pos        20  
#define RTC_TLR_10HR_Msk        (0x3ul << RTC_TLR_10HR_Pos)

#define RTC_TLR_1HR_Pos         16  
#define RTC_TLR_1HR_Msk         (0xFul << RTC_TLR_1HR_Pos)

#define RTC_TLR_10MIN_Pos       12  
#define RTC_TLR_10MIN_Msk       (0x7ul << RTC_TLR_10MIN_Pos)

#define RTC_TLR_1MIN_Pos        8  
#define RTC_TLR_1MIN_Msk        (0xFul << RTC_TLR_1MIN_Pos)

#define RTC_TLR_10SEC_Pos       4  
#define RTC_TLR_10SEC_Msk       (0x7ul << RTC_TLR_10SEC_Pos)

#define RTC_TLR_1SEC_Pos        0  
#define RTC_TLR_1SEC_Msk        (0xFul << RTC_TLR_1SEC_Pos)

/* RTC CLR Bit Field Definitions */
#define RTC_CLR_10YEAR_Pos      20  
#define RTC_CLR_10YEAR_Msk      (0xFul << RTC_CLR_10YEAR_Pos)

#define RTC_CLR_1YEAR_Pos       16  
#define RTC_CLR_1YEAR_Msk       (0xFul << RTC_CLR_1YEAR_Pos)

#define RTC_CLR_10MON_Pos       12  
#define RTC_CLR_10MON_Msk       (1ul << RTC_CLR_10MON_Pos)

#define RTC_CLR_1MON_Pos        8  
#define RTC_CLR_1MON_Msk        (0xFul << RTC_CLR_1MON_Pos)

#define RTC_CLR_10DAY_Pos       4  
#define RTC_CLR_10DAY_Msk       (0x3ul << RTC_CLR_10DAY_Pos)

#define RTC_CLR_1DAY_Pos        0  
#define RTC_CLR_1DAY_Msk        (0xFul << RTC_CLR_1DAY_Pos)

/* RTC TSSR Bit Field Definitions */
#define RTC_TSSR_24H_12H_Pos    0  
#define RTC_TSSR_24H_12H_Msk    (1ul << RTC_TSSR_24H_12H_Pos)

/* RTC DWR Bit Field Definitions */
#define RTC_DWR_DWR_Pos         0  
#define RTC_DWR_DWR_Msk         (0x7ul << RTC_DWR_DWR_Pos)

/* RTC TAR Bit Field Definitions */
#define RTC_TAR_10HR_Pos        20  
#define RTC_TAR_10HR_Msk        (0x3ul << RTC_TAR_10HR_Pos)

#define RTC_TAR_1HR_Pos         16  
#define RTC_TAR_1HR_Msk         (0xFul << RTC_TAR_1HR_Pos)

#define RTC_TAR_10MIN_Pos       12  
#define RTC_TAR_10MIN_Msk       (0x7ul << RTC_TAR_10MIN_Pos)

#define RTC_TAR_1MIN_Pos        8  
#define RTC_TAR_1MIN_Msk        (0xFul << RTC_TAR_1MIN_Pos)

#define RTC_TAR_10SEC_Pos       4  
#define RTC_TAR_10SEC_Msk       (0x7ul << RTC_TAR_10SEC_Pos)

#define RTC_TAR_1SEC_Pos        0  
#define RTC_TAR_1SEC_Msk        (0xFul << RTC_TAR_1SEC_Pos)

/* RTC CAR Bit Field Definitions */
#define RTC_CAR_10YEAR_Pos      20  
#define RTC_CAR_10YEAR_Msk      (0xFul << RTC_CAR_10YEAR_Pos)

#define RTC_CAR_1YEAR_Pos       16  
#define RTC_CAR_1YEAR_Msk       (0xFul << RTC_CAR_1YEAR_Pos)

#define RTC_CAR_10MON_Pos       12  
#define RTC_CAR_10MON_Msk       (1ul << RTC_CAR_10MON_Pos)

#define RTC_CAR_1MON_Pos        8  
#define RTC_CAR_1MON_Msk        (0xFul << RTC_CAR_1MON_Pos)

#define RTC_CAR_10DAY_Pos       4  
#define RTC_CAR_10DAY_Msk       (0x3ul << RTC_CAR_10DAY_Pos)

#define RTC_CAR_1DAY_Pos        0  
#define RTC_CAR_1DAY_Msk        (0xFul << RTC_CAR_1DAY_Pos)

/* RTC LIR Bit Field Definitions */
#define RTC_LIR_LIR_Pos         0  
#define RTC_LIR_LIR_Msk         (1ul << RTC_LIR_LIR_Pos)

/* RTC RIER Bit Field Definitions */
#define RTC_RIER_TIER_Pos       1  
#define RTC_RIER_TIER_Msk       (1ul << RTC_RIER_TIER_Pos)

#define RTC_RIER_AIER_Pos       0  
#define RTC_RIER_AIER_Msk       (1ul << RTC_RIER_AIER_Pos)

/* RTC RIIR Bit Field Definitions */
#define RTC_RIIR_TIF_Pos        1  
#define RTC_RIIR_TIF_Msk        (1ul << RTC_RIIR_TIF_Pos)

#define RTC_RIIR_AIF_Pos        0  
#define RTC_RIIR_AIF_Msk        (1ul << RTC_RIIR_AIF_Pos)

/* RTC TTR Bit Field Definitions */
#define RTC_TTR_TWKE_Pos        3  
#define RTC_TTR_TWKE_Msk        (1ul << RTC_TTR_TWKE_Pos)

#define RTC_TTR_TTR_Pos         0  
#define RTC_TTR_TTR_Msk         (0x7ul << RTC_TTR_TTR_Pos)


/*----------------------------- ADC Controller -------------------------------*/
typedef struct
{
    __I  uint32_t  RSLT:16;
    __I  uint32_t  OVERRUN:1;
    __I  uint32_t  VALID:1;
    __I  uint32_t  RESERVE1:14;
} ADC_ADDR_T;

typedef struct
{
    __IO uint32_t  ADEN:1;
    __IO uint32_t  ADIE:1;
    __IO uint32_t  ADMD:2;
    __IO uint32_t  TRGS:2;
    __IO uint32_t  TRGCOND:2;
    __IO uint32_t  TRGEN:1;
    __IO uint32_t  PTEN:1;
    __IO uint32_t  DIFFEN:1;
    __IO uint32_t  ADST:1;
    __I  uint32_t  RESERVE0:19;
    __IO uint32_t  DMOF:1;
} ADC_ADCR_T;

typedef struct
{
    __IO uint32_t  CHEN:8;
    __IO uint32_t  PRESEL:2;
    __I  uint32_t  RESERVE:22;
} ADC_ADCHER_T;

typedef struct
{
    __IO uint32_t  CMPEN:1;
    __IO uint32_t  CMPIE:1;
    __IO uint32_t  CMPCOND:1;
    __IO uint32_t  CMPCH:3;
    __I  uint32_t  RESERVE0:2;
    __IO uint32_t  CMPMATCNT:4;
    __I  uint32_t  RESERVE1:4;
    __IO uint32_t  CMPD:12;
    __I  uint32_t  RESERVE2:4;
} ADC_ADCMPR_T;

typedef struct
{
    __IO uint32_t  ADF:1;
    __IO uint32_t  CMPF0:1;
    __IO uint32_t  CMPF1:1;
    __I  uint32_t  BUSY:1;
    __I  uint32_t  CHANNEL:3;
    __I  uint32_t  RESERVE0:1;
    __I  uint32_t  VALID:8;
    __I  uint32_t  OVERRUN:8;
    __I  uint32_t  RESERVE1:8;
} ADC_ADSR_T;

typedef struct
{
    __IO uint32_t  CALEN:1;
    __I  uint32_t  CALDONE:1;
    __I  uint32_t  RESERVE:30;
} ADC_ADCALR_T;

typedef struct
{
    __IO uint32_t  AD_PDMA:12;
    __I  uint32_t  RESERVE:20;
} ADC_ADPDMA_T;

typedef struct
{
    union {
        __I uint32_t u32ADDR[8];
        struct {
            __I  uint32_t  RSLT:16;
            __I  uint32_t  OVERRUN:1;
            __I  uint32_t  VALID:1;
            __I  uint32_t  RESERVE1:14;
        } ADDR[8];
    };
    
    union {
        __IO uint32_t u32ADCR;
        struct {
            __IO uint32_t  ADEN:1;
            __IO uint32_t  ADIE:1;
            __IO uint32_t  ADMD:2;
            __IO uint32_t  TRGS:2;
            __IO uint32_t  TRGCOND:2;
            __IO uint32_t  TRGEN:1;
            __IO uint32_t  PTEN:1;
            __IO uint32_t  DIFFEN:1;
            __IO uint32_t  ADST:1;
            __I  uint32_t  RESERVE0:19;
            __IO uint32_t  DMOF:1;
        } ADCR;
    };
    
    union {
        __IO uint32_t u32ADCHER;
        struct {
            __IO uint32_t  CHEN:8;
            __IO uint32_t  PRESEL:2;
            __I  uint32_t  RESERVE:22;
        } ADCHER;
    };
    
    union {
        __IO uint32_t u32ADCMPR[2];
        struct {
            __IO uint32_t  CMPEN:1;
            __IO uint32_t  CMPIE:1;
nuc1xx.h - 源码说明

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