nuc1xx.h

cortex-m0 LCD1602程序

            __IO uint32_t  SS_LTRIG:1;
            __I  uint32_t  LTRIG_FLAG:1;
            __I  uint32_t  RESERVE:26;
        } SSR;
    };

    __I uint32_t RESERVE0;

    union {
        __I uint32_t u32RX[2];
        __I uint32_t RX[2];
    };

    __I uint32_t RESERVE1;
    __I uint32_t RESERVE2;

    union {
        __O uint32_t u32TX[2];
        __O uint32_t TX[2];
    };

    __I uint32_t RESERVE3;
    __I uint32_t RESERVE4;
    __I uint32_t RESERVE5;

    union {
        __IO uint32_t u32VARCLK;
        __IO uint32_t VARCLK;
    };

    union {
        __IO uint32_t u32DMA;
        struct {
            __IO uint32_t  TX_DMA_GO:1;
            __IO uint32_t  RX_DMA_GO:1;
            __I  uint32_t  RESERVE:30;
        } DMA;
    };

    union {
        __IO uint32_t u32CNTRL2;
        struct {
            __IO uint32_t  DIV_ONE:1;
            __I  uint32_t  RESERVE0:7;
            __IO uint32_t  NOSLVSEL:1;
            __IO uint32_t  SLV_ABORT:1;
            __IO uint32_t  SSTA_INTEN:1;
            __IO uint32_t  SLV_START_INTSTS:1;
            __I  uint32_t  RESERVE1:20;
        } CNTRL2;
    };

    union {
        __IO uint32_t u32FIFO_CTL;
        struct {
            __IO uint32_t  RX_CLR:1;
            __IO uint32_t  TX_CLR:1;
            __I  uint32_t  RESERVE0:30;
        } FIFO_CTL;
    };

} SPI_T;


/* SPI_CNTRL Bit Field Definitions */
#define SPI_CNTRL_TX_FULL_Pos      27
#define SPI_CNTRL_TX_FULL_Msk      (1ul << SPI_CNTRL_TX_FULL_Pos)

#define SPI_CNTRL_TX_EMPTY_Pos     26
#define SPI_CNTRL_TX_EMPTY_Msk     (1ul << SPI_CNTRL_TX_EMPTY_Pos)

#define SPI_CNTRL_RX_FULL_Pos      25
#define SPI_CNTRL_RX_FULL_Msk      (1ul << SPI_CNTRL_RX_FULL_Pos)

#define SPI_CNTRL_RX_EMPTY_Pos     24
#define SPI_CNTRL_RX_EMPTY_Msk     (1ul << SPI_CNTRL_RX_EMPTY_Pos)

#define SPI_CNTRL_VARCLK_EN_Pos    23
#define SPI_CNTRL_VARCLK_EN_Msk    (1ul << SPI_CNTRL_VARCLK_EN_Pos)

#define SPI_CNTRL_TWOB_Pos         22
#define SPI_CNTRL_TWOB_Msk         (1ul << SPI_CNTRL_TWOB_Pos)

#define SPI_CNTRL_FIFO_Pos         21
#define SPI_CNTRL_FIFO_Msk         (1ul << SPI_CNTRL_FIFO_Pos)

#define SPI_CNTRL_REORDER_Pos      19
#define SPI_CNTRL_REORDER_Msk      (3ul << SPI_CNTRL_REORDER_Pos)

#define SPI_CNTRL_SLAVE_Pos        18
#define SPI_CNTRL_SLAVE_Msk        (1ul << SPI_CNTRL_SLAVE_Pos)

#define SPI_CNTRL_IE_Pos           17
#define SPI_CNTRL_IE_Msk           (1ul << SPI_CNTRL_IE_Pos)

#define SPI_CNTRL_IF_Pos           16
#define SPI_CNTRL_IF_Msk           (1ul << SPI_CNTRL_IF_Pos)

#define SPI_CNTRL_SP_CYCLE_Pos     12
#define SPI_CNTRL_SP_CYCLE_Msk     (0xFul << SPI_CNTRL_SP_CYCLE_Pos)

#define SPI_CNTRL_CLKP_Pos         11
#define SPI_CNTRL_CLKP_Msk         (1ul << SPI_CNTRL_CLKP_Pos)

#define SPI_CNTRL_LSB_Pos          10
#define SPI_CNTRL_LSB_Msk          (1ul << SPI_CNTRL_LSB_Pos)

#define SPI_CNTRL_TX_NUM_Pos       8
#define SPI_CNTRL_TX_NUM_Msk       (3ul << SPI_CNTRL_TX_NUM_Pos)

#define SPI_CNTRL_TX_BIT_LEN_Pos   3
#define SPI_CNTRL_TX_BIT_LEN_Msk   (0x1Ful << SPI_CNTRL_TX_BIT_LEN_Pos)

#define SPI_CNTRL_TX_NEG_Pos       2
#define SPI_CNTRL_TX_NEG_Msk       (1ul << SPI_CNTRL_TX_NEG_Pos)

#define SPI_CNTRL_RX_NEG_Pos       1
#define SPI_CNTRL_RX_NEG_Msk       (1ul << SPI_CNTRL_RX_NEG_Pos)

#define SPI_CNTRL_GO_BUSY_Pos      0
#define SPI_CNTRL_GO_BUSY_Msk      (1ul << SPI_CNTRL_GO_BUSY_Pos)


/* SPI_DIVIDER Bit Field Definitions */
#define SPI_DIVIDER_DIVIDER2_Pos   16
#define SPI_DIVIDER_DIVIDER2_Msk   (0xFFFFul << SPI_DIVIDER_DIVIDER2_Pos)

#define SPI_DIVIDER_DIVIDER_Pos    0
#define SPI_DIVIDER_DIVIDE2_Msk    (0xFFFFul << SPI_DIVIDER_DIVIDER_Pos)

/* SPI_SSR Bit Field Definitions */
#define SPI_SSR_LTRIG_FLAG_Pos     5
#define SPI_SSR_LTRIG_FLAG_Msk     (1ul << SPI_SSR_LTRIG_FLAG_Pos)

#define SPI_SSR_SS_LTRIG_Pos       4
#define SPI_SSR_SS_LTRIG_Msk       (1ul << SPI_SSR_SS_LTRIG_Pos)

#define SPI_SSR_AUTOSS_Pos         3
#define SPI_SSR_AUTOSS_Msk         (1ul << SPI_SSR_AUTOSS_Pos)

#define SPI_SSR_SS_LVL_Pos         2
#define SPI_SSR_SS_LVL_Msk         (1ul << SPI_SSR_SS_LVL_Pos)

#define SPI_SSR_SSR_Pos            0
#define SPI_SSR_SSR_Msk            (3ul << SPI_SSR_SSR_Pos)

/* SPI_DMA Bit Field Definitions */
#define SPI_DMA_RX_DMA_GO_Pos   1
#define SPI_DMA_RX_DMA_GO_Msk   (1ul << SPI_DMA_RX_DMA_GO_Pos)

#define SPI_DMA_TX_DMA_GO_Pos   0
#define SPI_DMA_TX_DMA_GO_Msk   (1ul << SPI_DMA_TX_DMA_GO_Pos)

/* SPI_CNTRL2 Bit Field Definitions */
#define SPI_CNTRL2_SLV_START_INTSTS_Pos   11
#define SPI_CNTRL2_SLV_START_INTSTS_Msk   (1ul << SPI_CNTRL2_SLV_START_INTSTS_Pos)

#define SPI_CNTRL2_SSTA_INTEN_Pos   10
#define SPI_CNTRL2_SSTA_INTEN_Msk   (1ul << SPI_CNTRL2_SSTA_INTEN_Pos)

#define SPI_CNTRL2_SLV_ABORT_Pos    9
#define SPI_CNTRL2_SLV_ABORT_Msk    (1ul << SPI_CNTRL2_SLV_ABORT_Pos)

#define SPI_CNTRL2_NOSLVSEL_Pos     8
#define SPI_CNTRL2_NOSLVSEL_Msk     (1ul << SPI_CNTRL2_NOSLVSEL_Pos)

#define SPI_CNTRL2_DIV_ONE_Pos      0
#define SPI_CNTRL2_DIV_ONE_Msk      (1ul << SPI_CNTRL2_DIV_ONE_Pos)

/* SPI_FIFO_CTL Bit Field Definitions */
#define SPI_FIFO_CTL_TX_CLR_Pos   1
#define SPI_FIFO_CTL_TX_CLR_Msk   (1ul << SPI_FIFO_CTL_TX_CLR_Pos)

#define SPI_FIFO_CTL_RX_CLR_Pos   0
#define SPI_FIFO_CTL_RX_CLR_Msk   (1ul << SPI_FIFO_CTL_RX_CLR_Pos)


/*------------------------------ I2C Controller ------------------------------*/
typedef struct
{
    __I  uint32_t  RESERVE0:2;
    __IO uint32_t  AA:1;
    __IO uint32_t  SI:1;
    __IO uint32_t  STO:1;
    __IO uint32_t  STA:1;
    __IO uint32_t  ENS1:1;
    __IO uint32_t  EI:1;
    __I  uint32_t  RESERVE1:24;
} I2C_I2CON_T;

typedef struct
{
    __IO uint32_t  GC:1;
    __IO uint32_t  I2CADDR:7;
    __I  uint32_t  RESERVE:24;
} I2C_I2CADDR_T;

typedef __IO uint32_t I2C_I2CDAT_T;

typedef __I  uint32_t I2C_I2CSTATUS_T;

typedef __IO uint32_t I2C_I2CLK_T;

typedef struct
{
    __IO uint32_t  TIF:1;
    __IO uint32_t  DIV4:1;
    __IO uint32_t  ENTI:1;
    __I  uint32_t  RESERVE:29;
} I2C_I2CTOC_T;

typedef struct
{
    __I  uint32_t  RESERVE0:1;
    __IO uint32_t  I2CADM:7;
    __I  uint32_t  RESERVE1:24;
} I2C_I2CADM_T;

typedef struct
{
    union 
    {
        __IO uint32_t u32I2CON;
        
        struct 
        {
            __I  uint32_t  RESERVE0:2;
            __IO uint32_t  AA:1;
            __IO uint32_t  SI:1;
            __IO uint32_t  STO:1;
            __IO uint32_t  STA:1;
            __IO uint32_t  ENS1:1;
            __IO uint32_t  EI:1;
            __I  uint32_t  RESERVE1:24;
        } I2CON;
    };

    union 
    {
        __IO uint32_t u32I2CADDR0;
        
        struct 
        {
            __IO uint32_t  GC:1;
            __IO uint32_t  I2CADDR:7;
            __I  uint32_t  RESERVE:24;
        } I2CADDR0;
    };

    union 
    {
        __IO uint32_t u32I2CDAT;
        __IO uint32_t I2CDAT;
    };

    union 
    {
        __I uint32_t u32I2CSTATUS;
        __I uint32_t I2CSTATUS;
    };
    
    union 
    {
        __IO uint32_t u32I2CLK;
        __IO uint32_t I2CLK;
    };

    union 
    {
        __IO uint32_t u32I2CTOC;
        
        struct 
        {
            __IO uint32_t  TIF:1;
            __IO uint32_t  DIV4:1;
            __IO uint32_t  ENTI:1;
            __I  uint32_t  RESERVE:29;
        } I2CTOC;
    };

    union 
    {
        __IO uint32_t u32I2CADDR1;
        
        struct 
        {
            __IO uint32_t  GC:1;
            __IO uint32_t  I2CADDR:7;
            __I  uint32_t  RESERVE:24;
        } I2CADDR1;
    };
    
    union 
    {
        __IO uint32_t u32I2CADDR2;
        
        struct 
        {
            __IO uint32_t  GC:1;
            __IO uint32_t  I2CADDR:7;
            __I  uint32_t  RESERVE:24;
        } I2CADDR2;
    };    
    
    union 
    {
        __IO uint32_t u32I2CADDR3;
        
        struct 
        {
            __IO uint32_t  GC:1;
            __IO uint32_t  I2CADDR:7;
            __I  uint32_t  RESERVE:24;
        } I2CADDR3;
    }; 
    
    union 
    {
        __IO uint32_t u32I2CADM0;
        
        struct 
        {
            __I  uint32_t  RESERVE0:1;
            __IO uint32_t  I2CADM:7;
            __I  uint32_t  RESERVE1:24;
        } I2CADM0;
    };     
    
    union 
    {
        __IO uint32_t u32I2CADM1;
        
        struct 
        {
            __I  uint32_t  RESERVE0:1;
            __IO uint32_t  I2CADM:7;
            __I  uint32_t  RESERVE1:24;
        } I2CADM1;
    };

    union 
    {
        __IO uint32_t u32I2CADM2;
        
        struct 
        {
            __I  uint32_t  RESERVE0:1;
            __IO uint32_t  I2CADM:7;
            __I  uint32_t  RESERVE1:24;
        } I2CADM2;
    };
       
    union 
    {
        __IO uint32_t u32I2CADM3;
        
        struct 
        {
            __I  uint32_t  RESERVE0:1;
            __IO uint32_t  I2CADM:7;
            __I  uint32_t  RESERVE1:24;
        } I2CADM3;
    };       
} I2C_T;

/* I2C I2CON Bit Field Definitions */
#define I2C_I2CON_EI_Pos                        7
#define I2C_I2CON_EI_Msk                        (1ul << I2C_I2CON_EI_Pos)

#define I2C_I2CON_ENS1_Pos                      6
#define I2C_I2CON_ENS1_Msk                      (1ul << I2C_I2CON_ENS1_Pos)

#define I2C_I2CON_STA_Pos                       5
#define I2C_I2CON_STA_Msk                       (1ul << I2C_I2CON_STA_Pos)

#define I2C_I2CON_STO_Pos                       4
#define I2C_I2CON_STO_Msk                       (1ul << I2C_I2CON_STO_Pos)

#define I2C_I2CON_SI_Pos                        3
#define I2C_I2CON_SI_Msk                        (1ul << I2C_I2CON_SI_Pos)

#define I2C_I2CON_AA_Pos                        2
#define I2C_I2CON_AA_Msk                        (1ul << I2C_I2CON_AA_Pos)

/* I2C I2CADDR Bit Field Definitions */
#define I2C_I2CADDR_I2CADDR_Pos                 1
#define I2C_I2CADDR_I2CADDR_Msk                 (0x7Ful << I2C_I2CADDR_I2CADDR_Pos)

#define I2C_I2CADDR_GC_Pos                      0
#define I2C_I2CADDR_GC_Msk                      (1ul << I2C_I2CADDR_GC_Pos)

/* I2C I2CDAT Bit Field Definitions */
#define I2C_I2CDAT_I2CDAT_Pos                   0
#define I2C_I2CDAT_I2CDAT_Msk                   (0xFFul << I2C_I2CDAT_I2CDAT_Pos)

/* I2C I2CSTATUS Bit Field Definitions */
#define I2C_I2CSTATUS_I2CSTATUS_Pos             0
#define I2C_I2CSTATUS_I2CSTATUS_Msk             (0xFFul << I2C_I2CSTATUS_I2CSTATUS_Pos)

/* I2C I2CLK Bit Field Definitions */
#define I2C_I2CLK_I2CLK_Pos                     0
#define I2C_I2CLK_I2CLK_Msk                     (0xFFul << I2C_I2CLK_I2CLK_Pos)

/* I2C I2CTOC Bit Field Definitions */
#define I2C_I2CTOC_ENTI_Pos                     2
#define I2C_I2CTOC_ENTI_Msk                     (1ul << I2C_I2CTOC_ENTI_Pos)

#define I2C_I2CTOC_DIV4_Pos                     1
#define I2C_I2CTOC_DIV4_Msk                     (1ul << I2C_I2CTOC_DIV4_Pos)

#define I2C_I2CTOC_TIF_Pos                      0
#define I2C_I2CTOC_TIF_Msk                      (1ul << I2C_I2CTOC_TIF_Pos)

/* I2C I2CADM Bit Field Definitions */
#define I2C_I2CADM_I2CADM_Pos                   1
#define I2C_I2CADM_I2CADM_Msk                   (0x7Ful << I2C_I2CADM_I2CADM_Pos)


/*----------------------------- RTC Controller -------------------------------*/
typedef __IO uint32_t RTC_INIR_T;

typedef struct
{
    __IO uint32_t  AER:16;
    __I  uint32_t  ENF:1;
    __I  uint32_t  RESERVE1:15;
} RTC_AER_T;

typedef struct
{
    __IO uint32_t  FRACTION:6;
    __I  uint32_t  RESERVE0:2;
    __IO uint32_t  INTEGER:4;
    __I  uint32_t  RESERVE1:20;
} RTC_FCR_T;

typedef struct
{
    __IO uint32_t  SEC1:4;
    __IO uint32_t  SEC10:3;
    __I  uint32_t  RESERVE0:1;
    __IO uint32_t  MIN1:4;
    __IO uint32_t  MIN10:3;
    __I  uint32_t  RESERVE1:1;