nuc1xx.h

cortex-m0 LCD1602程序

#define UART_ISR_LIN_RX_BREAK_IF_Msk       (1ul << UART_ISR_LIN_RX_BREAK_IF_Pos)

#define UART_ISR_BUF_ERR_IF_Pos            5    
#define UART_ISR_BUF_ERR_IF_Msk            (1ul << UART_ISR_BUF_ERR_IF_Pos)

#define UART_ISR_TOUT_IF_Pos               4    
#define UART_ISR_TOUT_IF_Msk               (1ul << UART_ISR_TOUT_IF_Pos)

#define UART_ISR_MODEM_IF_Pos              3    
#define UART_ISR_MODEM_IF_Msk              (1ul << UART_ISR_MODEM_IF_Pos)

#define UART_ISR_RLS_IF_Pos                2    
#define UART_ISR_RLS_IF_Msk                (1ul << UART_ISR_RLS_IF_Pos)

#define UART_ISR_THRE_IF_Pos               1    
#define UART_ISR_THRE_IF_Msk               (1ul << UART_ISR_THRE_IF_Pos)

#define UART_ISR_RDA_IF_Pos                0    
#define UART_ISR_RDA_IF_Msk                (1ul << UART_ISR_RDA_IF_Pos)


/* UART TOR Bit Field Definitions */
#define UART_TOR_DLY_Pos          8
#define UART_TOR_DLY_Msk          (0xFFul << UART_TOR_DLY_Pos)

#define UART_TOR_TOIC_Pos         0
#define UART_TOR_TOIC_Msk         (0xFFul << UART_TOR_TOIC_Pos)

/* UART BAUD Bit Field Definitions */
#define UART_BAUD_DIV_X_EN_Pos    29
#define UART_BAUD_DIV_X_EN_Msk    (1ul << UART_BAUD_DIV_X_EN_Pos)

#define UART_BAUD_DIV_X_ONE_Pos   28
#define UART_BAUD_DIV_X_ONE_Msk   (1ul << UART_BAUD_DIV_X_ONE_Pos)

#define UART_BAUD_DIVIDER_X_Pos   24
#define UART_BAUD_DIVIDER_X_Msk   (0xFul << UART_BAUD_DIVIDER_X_Pos)

#define UART_BAUD_BRD_Pos         0
#define UART_BAUD_BRD_Msk         (0xFFul << UART_BAUD_BRD_Pos)

/* UART IRCR Bit Field Definitions */
#define UART_IRCR_INV_RX_Pos      6
#define UART_IRCR_INV_RX_Msk     (1ul << UART_IRCR_INV_RX_Pos)

#define UART_IRCR_INV_TX_Pos      5
#define UART_IRCR_INV_TX_Msk     (1ul << UART_IRCR_INV_TX_Pos)

#define UART_IRCR_TX_SELECT_Pos   1
#define UART_IRCR_TX_SELECT_Msk   (1ul << UART_IRCR_TX_SELECT_Pos)

/* UART ALT_CSR Bit Field Definitions */
#define UART_ALT_CSR_ADDR_MATCH_Pos      24
#define UART_ALT_CSR_ADDR_MATCH_Msk     (0xFFul << UART_ALT_CSR_ADDR_MATCH_Pos)

#define UART_ALT_CSR_RS485_ADD_EN_Pos   15
#define UART_ALT_CSR_RS485_ADD_EN_Msk   (1ul << UART_ALT_CSR_RS485_ADD_EN_Pos)

#define UART_ALT_CSR_RS485_AUD_Pos      10
#define UART_ALT_CSR_RS485_AUD_Msk      (1ul << UART_ALT_CSR_RS485_AUD_Pos)

#define UART_ALT_CSR_RS485_AAD_Pos      9
#define UART_ALT_CSR_RS485_AAD_Msk      (1ul << UART_ALT_CSR_RS485_AAD_Pos)

#define UART_ALT_CSR_RS485_NMM_Pos      8
#define UART_ALT_CSR_RS485_NMM_Msk      (1ul << UART_ALT_CSR_RS485_NMM_Pos)

#define UART_ALT_CSR_LIN_TX_EN_Pos      7
#define UART_ALT_CSR_LIN_TX_EN_Msk      (1ul << UART_ALT_CSR_LIN_TX_EN_Pos)

#define UART_ALT_CSR_LIN_RX_EN_Pos      6
#define UART_ALT_CSR_LIN_RX_EN_Msk      (1ul << UART_ALT_CSR_LIN_RX_EN_Pos)

#define UART_ALT_CSR_LIN_BKFL_Pos       0
#define UART_ALT_CSR_LIN_BKFL_Msk       (0xFul << UART_ALT_CSR_LIN_BKFL_Pos)

/* UART FUN_SEL Bit Field Definitions */
#define UART_FUN_SEL_FUN_SEL_Pos        0
#define UART_FUN_SEL_FUN_SEL_Msk       (0x3ul << UART_FUN_SEL_FUN_SEL_Pos)


/*----------------------------- Timer Controller -----------------------------*/
typedef struct
{
    __IO uint32_t  PRESCALE:8;
    __I  uint32_t  RESERVE0:8;
    __IO uint32_t  TDR_EN:1;
    __I  uint32_t  RESERVE1:7;
    __IO uint32_t  CTB:1;          
    __IO uint32_t  CACT:1;        
    __IO uint32_t  CRST:1;
    __IO uint32_t  MODE:2;
    __IO uint32_t  IE:1;
    __IO uint32_t  CEN:1;
    __IO uint32_t  DBGACK_TMR:1;
} TIMER_TCSR_T;

typedef __IO uint32_t TIMER_TCMPR_T;

typedef struct
{
    __IO uint32_t  TIF:1;
    __I  uint32_t  RESERVE:31;
} TIMER_TISR_T;

typedef __IO uint32_t TIMER_TDR_T;

typedef __IO uint32_t TIMER_TCAP_T;

typedef struct
{
    __IO uint32_t  TX_PHASE:1;
    __IO uint32_t  TEX_EDGE:2;
    __IO uint32_t  TEXEN:1;
    __IO uint32_t  RSTCAPSEL:1;
    __IO uint32_t  TEXIEN:1;
    __IO uint32_t  TEXDB:1;
    __IO uint32_t  TCDB:1;
    __I  uint32_t  RESERVE:24;
} TIMER_TEXCON_T;

typedef struct
{
    __IO uint32_t  TEXIF:1;
    __I  uint32_t  RESERVE:31;
} TIMER_TEXISR;

typedef struct
{
    union {
        __IO uint32_t u32TCSR;
        struct {
            __IO uint32_t  PRESCALE:8;
            __I  uint32_t  RESERVE0:8;
            __IO uint32_t  TDR_EN:1;
            __I  uint32_t  RESERVE1:7;
            __IO uint32_t  CTB:1;          
            __IO uint32_t  CACT:1;        
            __IO uint32_t  CRST:1;
            __IO uint32_t  MODE:2;
            __IO uint32_t  IE:1;
            __IO uint32_t  CEN:1;
            __IO uint32_t  DBGACK_TMR:1;
        } TCSR;
    };

    union {
        __IO uint32_t u32TCMPR;
        __IO uint32_t TCMPR;
    };

    union {
        __IO uint32_t u32TISR;
        struct {
            __IO uint32_t  TIF:1;
            __I  uint32_t  RESERVE:31;
        } TISR;
    };

    union {
        __IO uint32_t u32TDR;
        __IO uint32_t TDR;
    };

    union {
        __IO uint32_t u32TCAP;
        __IO uint32_t TCAP;
    };

    union {
        __IO uint32_t u32TEXCON;
        struct {
            __IO uint32_t  TX_PHASE:1;
            __IO uint32_t  TEX_EDGE:2;
            __IO uint32_t  TEXEN:1;
            __IO uint32_t  RSTCAPSEL:1;
            __IO uint32_t  TEXIEN:1;
            __IO uint32_t  TEXDB:1;
            __IO uint32_t  TCDB:1;
            __I  uint32_t  RESERVE:24;
        } TEXCON;
    };

    union {
        __IO uint32_t u32TEXISR;
        struct {
            __IO uint32_t  TEXIF:1;
            __I  uint32_t  RESERVE:31;
        } TEXISR;
    };
} TIMER_T;

/* Timer TCSR Bit Field Definitions */
#define TIMER_TCSR_DBGACK_TMR_Pos   31
#define TIMER_TCSR_DBGACK_TMR_Msk   (1ul << TIMER_TCSR_DBGACK_TMR_Pos)

#define TIMER_TCSR_CEN_Pos          30
#define TIMER_TCSR_CEN_Msk          (1ul << TIMER_TCSR_CEN_Pos)

#define TIMER_TCSR_IE_Pos           29
#define TIMER_TCSR_IE_Msk           (1ul << TIMER_TCSR_IE_Pos)

#define TIMER_TCSR_MODE_Pos         27
#define TIMER_TCSR_MODE_Msk         (0x3ul << TIMER_TCSR_MODE_Pos)

#define TIMER_TCSR_CRST_Pos         26
#define TIMER_TCSR_CRST_Msk         (1ul << TIMER_TCSR_CRST_Pos)

#define TIMER_TCSR_CACT_Pos         25
#define TIMER_TCSR_CACT_Msk         (1ul << TIMER_TCSR_CACT_Pos)

#define TIMER_TCSR_CTB_Pos          24
#define TIMER_TCSR_CTB_Msk          (1ul << TIMER_TCSR_CTB_Pos)

#define TIMER_TCSR_TDR_EN_Pos       16
#define TIMER_TCSR_TDR_EN_Msk       (1ul << TIMER_TCSR_TDR_EN_Pos)

#define TIMER_TCSR_PRESCALE_Pos     0
#define TIMER_TCSR_PRESCALE_Msk     (0xFFul << TIMER_TCSR_PRESCALE_Pos)

/* Timer TCMPR Bit Field Definitions */
#define TIMER_TCMP_Pos              0
#define TIMER_TCMP_Msk              (0xFFFFFFul << TIMER_TCMP_Pos)

/* Timer TISR Bit Field Definitions */
#define TIMER_TISR_TIF_Pos          0
#define TIMER_TISR_TIF_Msk          (1ul << TIMER_TISR_TIF_Pos)

/* Timer TDR Bit Field Definitions */
#define TIMER_TDR_Pos               0
#define TIMER_TDR_Msk               (0xFFFFFFul << TIMER_TDR_Pos)

/* Timer TCAP Bit Field Definitions */
#define TIMER_TCAP_Pos              0
#define TIMER_TCAP_Msk              (0xFFFFFFul << TIMER_TCAP_Pos)

/* Timer TEXCON Bit Field Definitions */
#define TIMER_TEXCON_TCDB_Pos       7
#define TIMER_TEXCON_TCDB_Msk       (1ul << TIMER_TEXCON_TCDB_Pos)

#define TIMER_TEXCON_TEXDB_Pos      6
#define TIMER_TEXCON_TEXDB_Msk      (1ul << TIMER_TEXCON_TEXDB_Pos)

#define TIMER_TEXCON_TEXIEN_Pos     5
#define TIMER_TEXCON_TEXIEN_Msk     (1ul << TIMER_TEXCON_TEXIEN_Pos)

#define TIMER_TEXCON_RSTCAPSEL_Pos  4
#define TIMER_TEXCON_RSTCAPSEL_Msk  (1ul << TIMER_TEXCON_RSTCAPSEL_Pos)

#define TIMER_TEXCON_TEXEN_Pos      3
#define TIMER_TEXCON_TEXEN_Msk      (1ul << TIMER_TEXCON_TEXEN_Pos)

#define TIMER_TEXCON_TEX_EDGE_Pos   1
#define TIMER_TEXCON_TEX_EDGE_Msk   (0x3ul << TIMER_TEXCON_TEX_EDGE_Pos)

#define TIMER_TEXCON_TX_PHASE_Pos   0
#define TIMER_TEXCON_TX_PHASE_Msk   (1ul << TIMER_TEXCON_TX_PHASE_Pos)

/* Timer TEXISR Bit Field Definitions */
#define TIMER_TEXISR_TEXIF_Pos      0
#define TIMER_TEXISR_TEXIF_Msk      (1ul << TIMER_TEXISR_TEXIF_Pos)


/*----------------------------- WDT Controller -----------------------------*/
typedef struct
{
    __IO uint32_t  WTR:1;
    __IO uint32_t  WTRE:1;
    __IO uint32_t  WTRF:1;
    __IO uint32_t  WTIF:1;
    __IO uint32_t  WTWKE:1;
    __IO uint32_t  WTWKF:1;
    __IO uint32_t  WTIE:1;
    __IO uint32_t  WTE:1;
    __IO uint32_t  WTIS:3;
    __I  uint32_t  RESERVE1:20;
    __IO uint32_t  DBGACK_WDT:1;
} WDT_WTCR_T;

typedef struct
{
    union {
        __IO uint32_t u32WTCR;
        struct {
            __IO uint32_t  WTR:1;
            __IO uint32_t  WTRE:1;
            __IO uint32_t  WTRF:1;
            __IO uint32_t  WTIF:1;
            __IO uint32_t  WTWKE:1;
            __IO uint32_t  WTWKF:1;
            __IO uint32_t  WTIE:1;
            __IO uint32_t  WTE:1;
            __IO uint32_t  WTIS:3;
            __I  uint32_t  RESERVE1:20;
            __IO uint32_t  DBGACK_WDT:1;
        } WTCR;
    };
} WDT_T;

/* WDT WTCR Bit Field Definitions */
#define WDT_WTCR_DBGACK_WDT_Pos 31
#define WDT_WTCR_DBGACK_WDT_Msk (1ul << WDT_WTCR_DBGACK_WDT_Pos)

#define WDT_WTCR_WTIS_Pos       8  
#define WDT_WTCR_WTIS_Msk       (0x3ul << WDT_WTCR_WTIS_Pos)

#define WDT_WTCR_WTE_Pos        7  
#define WDT_WTCR_WTE_Msk        (1ul << WDT_WTCR_WTE_Pos)

#define WDT_WTCR_WTIE_Pos       6  
#define WDT_WTCR_WTIE_Msk       (1ul << WDT_WTCR_WTIE_Pos)

#define WDT_WTCR_WTWKF_Pos      5  
#define WDT_WTCR_WTWKF_Msk      (1ul << WDT_WTCR_WTWKF_Pos)

#define WDT_WTCR_WTWKE_Pos      4  
#define WDT_WTCR_WTWKE_Msk      (1ul << WDT_WTCR_WTWKE_Pos)

#define WDT_WTCR_WTIF_Pos       3  
#define WDT_WTCR_WTIF_Msk       (1ul << WDT_WTCR_WTIF_Pos)

#define WDT_WTCR_WTRF_Pos       2  
#define WDT_WTCR_WTRF_Msk       (1ul << WDT_WTCR_WTRF_Pos)

#define WDT_WTCR_WTRE_Pos       1  
#define WDT_WTCR_WTRE_Msk       (1ul << WDT_WTCR_WTRE_Pos)

#define WDT_WTCR_WTR_Pos        0  
#define WDT_WTCR_WTR_Msk        (1ul << WDT_WTCR_WTR_Pos)


/*------------------------- SPI Interface Controller -------------------------*/
typedef struct
{
    __IO uint32_t  GO_BUSY:1;
    __IO uint32_t  RX_NEG:1;
    __IO uint32_t  TX_NEG:1;
    __IO uint32_t  TX_BIT_LEN:5;
    __IO uint32_t  TX_NUM:2;
    __IO uint32_t  LSB:1;
    __IO uint32_t  CLKP:1;
    __IO uint32_t  SP_CYCLE:4;
    __IO uint32_t  IF:1;
    __IO uint32_t  IE:1;
    __IO uint32_t  SLAVE:1;
    __IO uint32_t  REORDER:2;
    __IO uint32_t  FIFO:1;
    __IO uint32_t  TWOB:1;
    __IO uint32_t  VARCLK_EN:1;
    __I  uint32_t  RX_EMPTY:1;
    __I  uint32_t  RX_FULL:1;
    __I  uint32_t  TX_EMPTY:1;
    __I  uint32_t  TX_FULL:1;
    __I  uint32_t  RESERVE:4;
} SPI_CNTRL_T;

typedef struct
{
    __IO uint32_t  DIVIDER:16;
    __IO uint32_t  DIVIDER2:16;
} SPI_DIVIDER_T;

typedef struct
{
    __IO uint32_t  SSR:2;
    __IO uint32_t  SS_LVL:1;
    __IO uint32_t  AUTOSS:1;
    __IO uint32_t  SS_LTRIG:1;
    __I  uint32_t  LTRIG_FLAG:1;
    __I  uint32_t  RESERVE:26;
} SPI_SSR_T;


typedef __I  uint32_t   SPI_RX_T;
typedef __O  uint32_t   SPI_TX_T;
typedef __IO uint32_t   SPI_VARCLK_T;

typedef struct
{
    __IO uint32_t  TX_DMA_GO:1;
    __IO uint32_t  RX_DMA_GO:1;
    __I  uint32_t  RESERVE:30;
} SPI_DMA_T;

typedef struct
{
    __IO uint32_t  DIV_ONE:1;
    __I  uint32_t  RESERVE0:7;
    __IO uint32_t  NOSLVSEL:1;
    __IO uint32_t  SLV_ABORT:1;
    __IO uint32_t  SSTA_INTEN:1;
    __IO uint32_t  SLV_START_INTSTS:1;
    __I  uint32_t  RESERVE1:20;
} SPI_CNTRL2_T;

typedef struct
{
    __IO uint32_t  RX_CLR:1;
    __IO uint32_t  TX_CLR:1;
    __I  uint32_t  RESERVE0:30;
} SPI_FIFO_CTL_T;

typedef struct
{
    union {
        __IO uint32_t u32CNTRL;
        struct {
            __IO uint32_t  GO_BUSY:1;
            __IO uint32_t  RX_NEG:1;
            __IO uint32_t  TX_NEG:1;
            __IO uint32_t  TX_BIT_LEN:5;
            __IO uint32_t  TX_NUM:2;
            __IO uint32_t  LSB:1;
            __IO uint32_t  CLKP:1;
            __IO uint32_t  SP_CYCLE:4;
            __IO uint32_t  IF:1;
            __IO uint32_t  IE:1;
            __IO uint32_t  SLAVE:1;
            __IO uint32_t  REORDER:2;
            __IO uint32_t  FIFO:1;
            __IO uint32_t  TWOB:1;
            __IO uint32_t  VARCLK_EN:1;
            __I  uint32_t  RX_EMPTY:1;
            __I  uint32_t  RX_FULL:1;
            __I  uint32_t  TX_EMPTY:1;
            __I  uint32_t  TX_FULL:1;
            __I  uint32_t  RESERVE:4;
        } CNTRL;
    };

    union {
        __IO uint32_t u32DIVIDER;
        struct {
            __IO uint32_t  DIVIDER:16;
            __IO uint32_t  DIVIDER2:16;
        } DIVIDER;
    };

    union {
        __IO uint32_t u32SSR;
        struct {
            __IO uint32_t  SSR:2;
            __IO uint32_t  SS_LVL:1;
            __IO uint32_t  AUTOSS:1;