📄 nuc1xx.h
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/*---------------------------------------------------------------------------------------------------------*/
/* */
/* Copyright (c) Nuvoton Technology Corp. All rights reserved. */
/* */
/*---------------------------------------------------------------------------------------------------------*/
#ifndef __NUC1xx_H__
#define __NUC1xx_H__
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
/************************ NUC1xx Interrupt Numbers ************************************************/
BOD_IRQn = 0,
WDT_IRQn = 1,
EINT0_IRQn = 2,
EINT1_IRQn = 3,
GPAB_IRQn = 4,
GPCDE_IRQn = 5,
PWMA_IRQn = 6,
PWMB_IRQn = 7,
TMR0_IRQn = 8,
TMR1_IRQn = 9,
TMR2_IRQn = 10,
TMR3_IRQn = 11,
UART0_IRQn = 12,
UART1_IRQn = 13,
SPI0_IRQn = 14,
SPI1_IRQn = 15,
SPI2_IRQn = 16,
SPI3_IRQn = 17,
I2C0_IRQn = 18,
I2C1_IRQn = 19,
CAN0_IRQn = 20,
CAN1_IRQn = 21,
SD_IRQn = 22,
USBD_IRQn = 23,
PS2_IRQn = 24,
ACMP_IRQn = 25,
PDMA_IRQn = 26,
I2S_IRQn = 27,
PWRWU_IRQn = 28,
ADC_IRQn = 29,
DAC_IRQn = 30,
RTC_IRQn = 31
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M0 Processor and Core Peripherals */
#define __MPU_PRESENT 0 /*!< armikcmu does not provide a MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< armikcmu Supports 2 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
#include "system_NUC1xx.h" /* NUC1xx System */
#include "System\SysInfra.h"
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
/*--------------------- General Purpose Input and Ouptut ---------------------*/
typedef struct
{
__IO uint32_t PMD0:2;
__IO uint32_t PMD1:2;
__IO uint32_t PMD2:2;
__IO uint32_t PMD3:2;
__IO uint32_t PMD4:2;
__IO uint32_t PMD5:2;
__IO uint32_t PMD6:2;
__IO uint32_t PMD7:2;
__IO uint32_t PMD8:2;
__IO uint32_t PMD9:2;
__IO uint32_t PMD10:2;
__IO uint32_t PMD11:2;
__IO uint32_t PMD12:2;
__IO uint32_t PMD13:2;
__IO uint32_t PMD14:2;
__IO uint32_t PMD15:2;
} GPIO_PMD_T;
typedef __IO uint32_t GPIO_OFFD_T;
typedef __IO uint32_t GPIO_DOUT_T;
typedef __IO uint32_t GPIO_DMASK_T;
typedef __IO uint32_t GPIO_PIN_T;
typedef __IO uint32_t GPIO_DBEN_T;
typedef __IO uint32_t GPIO_IMD_T;
typedef __IO uint32_t GPIO_IEN_T;
typedef __IO uint32_t GPIO_ISRC_T;
typedef struct
{
union {
__IO uint32_t u32PMD;
struct {
__IO uint32_t PMD0:2;
__IO uint32_t PMD1:2;
__IO uint32_t PMD2:2;
__IO uint32_t PMD3:2;
__IO uint32_t PMD4:2;
__IO uint32_t PMD5:2;
__IO uint32_t PMD6:2;
__IO uint32_t PMD7:2;
__IO uint32_t PMD8:2;
__IO uint32_t PMD9:2;
__IO uint32_t PMD10:2;
__IO uint32_t PMD11:2;
__IO uint32_t PMD12:2;
__IO uint32_t PMD13:2;
__IO uint32_t PMD14:2;
__IO uint32_t PMD15:2;
} PMD;
};
union {
__IO uint32_t u32OFFD;
__IO uint32_t OFFD;
};
union {
__IO uint32_t u32DOUT;
__IO uint32_t DOUT;
};
union {
__IO uint32_t u32DMASK;
__IO uint32_t DMASK;
};
union {
__IO uint32_t u32PIN;
__IO uint32_t PIN;
};
union {
__IO uint32_t u32DBEN;
__IO uint32_t DBEN;
};
union {
__IO uint32_t u32IMD;
__IO uint32_t IMD;
};
union {
__IO uint32_t u32IEN;
__IO uint32_t IEN;
};
union {
__IO uint32_t u32ISRC;
__IO uint32_t ISRC;
};
} GPIO_T;
typedef struct
{
union {
__IO uint32_t u32DBNCECON;
struct {
__IO uint32_t DBCLKSEL:4;
__IO uint32_t DBCLKSRC:1;
__IO uint32_t ICLK_ON:1;
__I uint32_t RESERVE:26;
} DBNCECON;
};
} GPIO_DBNCECON_T;
/* GPIO PMD Bit Field Definitions */
#define GPIO_PMD_PMD15_Pos 30
#define GPIO_PMD_PMD15_Msk (0x3ul << GPIO_PMD_PMD15_Pos)
#define GPIO_PMD_PMD14_Pos 28
#define GPIO_PMD_PMD14_Msk (0x3ul << GPIO_PMD_PMD14_Pos)
#define GPIO_PMD_PMD13_Pos 26
#define GPIO_PMD_PMD13_Msk (0x3ul << GPIO_PMD_PMD13_Pos)
#define GPIO_PMD_PMD12_Pos 24
#define GPIO_PMD_PMD12_Msk (0x3ul << GPIO_PMD_PMD12_Pos)
#define GPIO_PMD_PMD11_Pos 22
#define GPIO_PMD_PMD11_Msk (0x3ul << GPIO_PMD_PMD11_Pos)
#define GPIO_PMD_PMD10_Pos 20
#define GPIO_PMD_PMD10_Msk (0x3ul << GPIO_PMD_PMD10_Pos)
#define GPIO_PMD_PMD9_Pos 18
#define GPIO_PMD_PMD9_Msk (0x3ul << GPIO_PMD_PMD9_Pos)
#define GPIO_PMD_PMD8_Pos 16
#define GPIO_PMD_PMD8_Msk (0x3ul << GPIO_PMD_PMD8_Pos)
#define GPIO_PMD_PMD7_Pos 14
#define GPIO_PMD_PMD7_Msk (0x3ul << GPIO_PMD_PMD7_Pos)
#define GPIO_PMD_PMD6_Pos 12
#define GPIO_PMD_PMD6_Msk (0x3ul << GPIO_PMD_PMD6_Pos)
#define GPIO_PMD_PMD5_Pos 10
#define GPIO_PMD_PMD5_Msk (0x3ul << GPIO_PMD_PMD5_Pos)
#define GPIO_PMD_PMD4_Pos 8
#define GPIO_PMD_PMD4_Msk (0x3ul << GPIO_PMD_PMD4_Pos)
#define GPIO_PMD_PMD3_Pos 6
#define GPIO_PMD_PMD3_Msk (0x3ul << GPIO_PMD_PMD3_Pos)
#define GPIO_PMD_PMD2_Pos 4
#define GPIO_PMD_PMD2_Msk (0x3ul << GPIO_PMD_PMD2_Pos)
#define GPIO_PMD_PMD1_Pos 2
#define GPIO_PMD_PMD1_Msk (0x3ul << GPIO_PMD_PMD1_Pos)
#define GPIO_PMD_PMD0_Pos 0
#define GPIO_PMD_PMD0_Msk (0x3ul << GPIO_PMD_PMD0_Pos)
/* GPIO OFFD Bit Field Definitions */
#define GPIO_OFFD_Pos 16
#define GPIO_OFFD_Msk (0xFFFFul << GPIO_OFFD_Pos)
/* GPIO DOUT Bit Field Definitions */
#define GPIO_DOUT_Pos 0
#define GPIO_DOUT_Msk (0xFFFFul << GPIO_DOUT_Pos)
/* GPIO DMASK Bit Field Definitions */
#define GPIO_DMASK_Pos 0
#define GPIO_DMASK_Msk (0xFFFFul << GPIO_DMASK_Pos)
/* GPIO PIN Bit Field Definitions */
#define GPIO_PIN_Pos 0
#define GPIO_PIN_Msk (0xFFFFul << GPIO_PIN_Pos)
/* GPIO DBEN Bit Field Definitions */
#define GPIO_DBEN_Pos 0
#define GPIO_DBEN_Msk (0xFFFFul << GPIO_DBEN_Pos)
/* GPIO IMD Bit Field Definitions */
#define GPIO_IMD_Pos 0
#define GPIO_IMD_Msk (0xFFFFul << GPIO_IMD_Pos)
/* GPIO IEN Bit Field Definitions */
#define GPIO_IEN_IR_EN_Pos 16
#define GPIO_IEN_IR_EN_Msk (0xFFFFul << GPIO_IEN_IR_EN_Pos)
#define GPIO_IEN_IF_EN_Pos 0
#define GPIO_IEN_IF_EN_Msk (0xFFFFul << GPIO_IEN_IF_EN_Pos)
/* GPIO ISRC Bit Field Definitions */
#define GPIO_ISRC_Pos 0
#define GPIO_ISRC_Msk (0xFFFFul << GPIO_ISRC_Pos)
/* GPIO DBNCECON Bit Field Definitions */
#define GPIO_DBNCECON_ICLK_ON_Pos 5
#define GPIO_DBNCECON_ICLK_ON_Msk (1ul << GPIO_DBNCECON_ICLK_ON_Pos)
#define GPIO_DBNCECON_DBCLKSRC_Pos 4
#define GPIO_DBNCECON_DBCLKSRC_Msk (1ul << GPIO_DBNCECON_DBCLKSRC_Pos)
#define GPIO_DBNCECON_DBCLKSEL_Pos 0
#define GPIO_DBNCECON_DBCLKSEL_Msk (0xFul << GPIO_DBNCECON_DBCLKSEL_Pos)
/* GPIO Port[x] Pin I/O Bit Output/Input Control Bit Field Definitions */
#define GPIO_GPIOx_DOUT_Pos 0
#define GPIO_GPIOx_DOUT_Msk (1ul << GPIO_GPIOx_DOUT_Pos)
/*------------------------- UART Interface Controller ------------------------*/
typedef __IO uint32_t UART_DATA_T;
typedef struct
{
__IO uint32_t RDA_IEN:1;
__IO uint32_t THRE_IEN:1;
__IO uint32_t RLS_IEN:1;
__IO uint32_t MODEM_IEN:1;
__IO uint32_t RTO_IEN:1;
__IO uint32_t BUF_ERR_IEN:1;
__IO uint32_t WAKE_EN:1;
__I uint32_t RESERVE0:1;
__IO uint32_t LIN_RX_BRK_IEN:1;
__I uint32_t RESERVE1:2;
__IO uint32_t TIME_OUT_EN:1; /* Time-out counter enable */
__IO uint32_t AUTO_RTS_EN:1;
__IO uint32_t AUTO_CTS_EN:1;
__IO uint32_t DMA_TX_EN:1;
__IO uint32_t DMA_RX_EN:1;
__I uint32_t RESERVE2:16;
} UART_IER_T;
typedef struct
{
__I uint32_t RESERVE0:1;
__IO uint32_t RFR:1;
__IO uint32_t TFR:1;
__I uint32_t RESERVE1:1;
__IO uint32_t RFITL:4; /* Rx FIFO Interrupt Trigger Level */
__IO uint32_t RX_DIS:1;
__I uint32_t RESERVE2:7;
__IO uint32_t RTS_TRI_LEV:4;
__I uint32_t RESERVE3:12;
} UART_FCR_T;
typedef struct
{
__IO uint32_t WLS:2; /* Word length select */
__IO uint32_t NSB:1; /* Number of STOP bit */
__IO uint32_t PBE:1; /* Parity bit enable */
__IO uint32_t EPE:1; /* Even parity enable */
__IO uint32_t SPE:1; /* Stick parity enable*/
__IO uint32_t BCB:1; /* Break control bit */
__I uint32_t RESERVE:25;
} UART_LCR_T;
typedef struct
{
__I uint32_t RESERVE0:1;
__IO uint32_t RTS:1;
__I uint32_t RESERVE1:2;
__IO uint32_t LBME:1;
__I uint32_t RESERVE2:4;
__IO uint32_t LEV_RTS:1;
__I uint32_t RESERVE3:3;
__I uint32_t RTS_ST:1; /* RTS status */
__I uint32_t RESERVE4:18;
} UART_MCR_T;
typedef struct
{
__IO uint32_t DCTSF:1;
__I uint32_t RESERVE0:3;
__I uint32_t CTS_ST:1; /* CTS status */
__I uint32_t RESERVE1:3;
__IO uint32_t LEV_CTS:1;
__I uint32_t RESERVE2:23;
} UART_MSR_T;
typedef struct
{
__IO uint32_t RX_OVER_IF:1;
__I uint32_t RESERVE0:2;
__IO uint32_t RS485_ADD_DETF:1;
__IO uint32_t PEF:1;
__IO uint32_t FEF:1;
__IO uint32_t BIF:1;
__I uint32_t RESERVE1:1;
__I uint32_t RX_POINTER:6;
__I uint32_t RX_EMPTY:1;
__I uint32_t RX_FULL:1;
__I uint32_t TX_POINTER:6;
__I uint32_t TX_EMPTY:1;
__I uint32_t TX_FULL:1;
__IO uint32_t TX_OVER_IF:1;
__I uint32_t RESERVE2:3;
__I uint32_t TE_FLAG:1; /* Transmitter empty flag */
__I uint32_t RESERVE3:3;
} UART_FSR_T;
typedef struct
{
__IO uint32_t RDA_IF:1;
__IO uint32_t THRE_IF:1;
__IO uint32_t RLS_IF:1;
__IO uint32_t MODEM_IF:1;
__IO uint32_t TOUT_IF:1;
__IO uint32_t BUF_ERR_IF:1;
__I uint32_t RESERVE0:1;
__IO uint32_t LIN_RX_BREAK_IF:1;
__IO uint32_t RDA_INT:1;
__IO uint32_t THRE_INT:1;
__IO uint32_t RLS_INT:1;
__IO uint32_t MODEM_INT:1;
__IO uint32_t TOUT_INT:1;
__IO uint32_t BUF_ERR_INT:1;
__I uint32_t RESERVE1:1;
__IO uint32_t LIN_RX_BREAK_INT:1;
__I uint32_t RESERVE2:2;
__IO uint32_t HW_RLS_IF:1;
__IO uint32_t HW_MODEM_IF:1;
__IO uint32_t HW_TOUT_IF:1;
__IO uint32_t HW_BUF_ERR_IF:1;
__IO uint32_t RESERVE3:1;
__IO uint32_t HW_LIN_RX_BREAK_IF:1;
__I uint32_t RESERVE4:2;
__IO uint32_t HW_RLS_INT:1;
__IO uint32_t HW_MODEM_INT:1;
__IO uint32_t HW_TOUT_INT:1;
__IO uint32_t HW_BUF_ERR_INT:1;
__IO uint32_t RESERVE5:1;
__IO uint32_t HW_LIN_RX_BREAK_INT:1;
} UART_ISR_T;
typedef struct
{
__IO uint32_t TOIC:7;
__I uint32_t RESERVE0:1;
__IO uint32_t DLY:8;
__I uint32_t RESERVE1:16;
} UART_TOR_T;
typedef struct
{
__IO uint32_t BRD:16;
__I uint32_t RESERVE0:8;
__IO uint32_t DIVIDER_X:4;
__IO uint32_t DIV_X_ONE:1;
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