altivec.igen

gdb-6.0 linux 下的调试工具

	int i;
	unsigned32 f;
	sim_fpu op;
	for (i = 0; i < 4; i++) {
	  sim_fpu_32to (&op, (*vB).w[i]);
	  sim_fpu_round_32(&op, sim_fpu_round_down, sim_fpu_denorm_default);
	  sim_fpu_to32 (&f, &op);
	  (*vS).w[i] = f;
	}
	PPC_INSN_VR(VS_BITMASK, VB_BITMASK);

0.4,6.VS,11.0,16.VB,21.522:VX:av:vrfin %VD, %VB:Vector Round to Floating-Point Integer Nearest
	int i;
	unsigned32 f;
	sim_fpu op;
	for (i = 0; i < 4; i++) {
	  sim_fpu_32to (&op, (*vB).w[i]);
	  sim_fpu_round_32(&op, sim_fpu_round_near, sim_fpu_denorm_default);
	  sim_fpu_to32 (&f, &op);
	  (*vS).w[i] = f;
	}
	PPC_INSN_VR(VS_BITMASK, VB_BITMASK);

0.4,6.VS,11.0,16.VB,21.650:VX:av:vrfip %VD, %VB:Vector Round to Floating-Point Integer towards Plus Infinity
	int i;
	unsigned32 f;
	sim_fpu op;
	for (i = 0; i < 4; i++) {
	  sim_fpu_32to (&op, (*vB).w[i]);
	  sim_fpu_round_32(&op, sim_fpu_round_up, sim_fpu_denorm_default);
	  sim_fpu_to32 (&f, &op);
	  (*vS).w[i] = f;
	}
	PPC_INSN_VR(VS_BITMASK, VB_BITMASK);

0.4,6.VS,11.0,16.VB,21.586:VX:av:vrfiz %VD, %VB:Vector Round to Floating-Point Integer towards Zero
	int i;
	unsigned32 f;
	sim_fpu op;
	for (i = 0; i < 4; i++) {
	  sim_fpu_32to (&op, (*vB).w[i]);
	  sim_fpu_round_32(&op, sim_fpu_round_zero, sim_fpu_denorm_default);
	  sim_fpu_to32 (&f, &op);
	  (*vS).w[i] = f;
	}
	PPC_INSN_VR(VS_BITMASK, VB_BITMASK);


#
# Vector Rotate Left instructions, 6-128 ... 6-130
#

0.4,6.VS,11.VA,16.VB,21.4:VX:av:vrlb %VD, %VA, %VB:Vector Rotate Left Integer Byte
	int i;
	unsigned16 temp;
	for (i = 0; i < 16; i++) {
	  temp = (unsigned16)(*vA).b[i] << (((*vB).b[i]) & 7);
	  (*vS).b[i] = (temp & 0xff) | ((temp >> 8) & 0xff);
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.68:VX:av:vrlh %VD, %VA, %VB:Vector Rotate Left Integer Half Word
	int i;
	unsigned32 temp;
	for (i = 0; i < 8; i++) {
	  temp = (unsigned32)(*vA).h[i] << (((*vB).h[i]) & 0xf);
	  (*vS).h[i] = (temp & 0xffff) | ((temp >> 16) & 0xffff);
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.132:VX:av:vrlw %VD, %VA, %VB:Vector Rotate Left Integer Word
	int i;
	unsigned64 temp;
	for (i = 0; i < 4; i++) {
	  temp = (unsigned64)(*vA).w[i] << (((*vB).w[i]) & 0x1f);
	  (*vS).w[i] = (temp & 0xffffffff) | ((temp >> 32) & 0xffffffff);
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);


#
# Vector Conditional Select instruction, 6-133
#

0.4,6.VS,11.VA,16.VB,21.VC,26.42:VAX:av:vsel %VD, %VA, %VB, %VC:Vector Conditional Select
	int i;
	unsigned32 c;
	for (i = 0; i < 4; i++) {
	  c = (*vC).w[i];
	  (*vS).w[i] = ((*vB).w[i] & c) | ((*vA).w[i] & ~c);
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK);

#
# Vector Shift Left instructions, 6-134 ... 6-139
#

0.4,6.VS,11.VA,16.VB,21.452:VX:av:vsl %VD, %VA, %VB:Vector Shift Left
	int sh, i, j, carry, new_carry;
	sh = (*vB).b[0] & 7;	/* don't bother checking everything */
	carry = 0;
	for (j = 3; j >= 0; j--) {
	  if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
	    i = j;
	  else
	    i = (j + 2) % 4;
	  new_carry = (*vA).w[i] >> (32 - sh);
	  (*vS).w[i] = ((*vA).w[i] << sh) | carry;
	  carry = new_carry;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.260:VX:av:vslb %VD, %VA, %VB:Vector Shift Left Integer Byte
	int i, sh;
	for (i = 0; i < 16; i++) {
	  sh = ((*vB).b[i]) & 7;
	  (*vS).b[i] = (*vA).b[i] << sh;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.0,22.SH,26.44:VX:av:vsldol %VD, %VA, %VB:Vector Shift Left Double by Octet Immediate
	int i, j;
	for (j = 0, i = SH; i < 16; i++)
	  (*vS).b[j++] = (*vA).b[i];
	for (i = 0; i < SH; i++)
	  (*vS).b[j++] = (*vB).b[i];
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.324:VX:av:vslh %VD, %VA, %VB:Vector Shift Left Half Word
	int i, sh;
	for (i = 0; i < 8; i++) {
	  sh = ((*vB).h[i]) & 0xf;
	  (*vS).h[i] = (*vA).h[i] << sh;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.1036:VX:av:vslo %VD, %VA, %VB:Vector Shift Left by Octet
	int i, sh;
	if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
	  sh = ((*vB).b[AV_BINDEX(15)] >> 3) & 0xf;
	else
	  sh = ((*vB).b[AV_BINDEX(0)] >> 3) & 0xf;
	for (i = 0; i < 16; i++) {
	  if (15 - i > sh)
	    (*vS).b[AV_BINDEX(i)] = (*vA).b[AV_BINDEX(i + sh)];
	  else
	    (*vS).b[AV_BINDEX(i)] = 0;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.388:VX:av:vslw %VD, %VA, %VB:Vector Shift Left Integer Word
	int i, sh;
	for (i = 0; i < 4; i++) {
	  sh = ((*vB).w[i]) & 0x1f;
	  (*vS).w[i] = (*vA).w[i] << sh;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);


#
# Vector Splat instructions, 6-140 ... 6-145
#

0.4,6.VS,11.UIMM,16.VB,21.524:VX:av:vspltb %VD, %VB, %UIMM:Vector Splat Byte
	int i;
	unsigned8 b;
	b = (*vB).b[AV_BINDEX(UIMM & 0xf)];
	for (i = 0; i < 16; i++)
	  (*vS).b[i] = b;
	PPC_INSN_VR(VS_BITMASK, VB_BITMASK);

0.4,6.VS,11.UIMM,16.VB,21.588:VX:av:vsplth %VD, %VB, %UIMM:Vector Splat Half Word
	int i;
	unsigned16 h;
	h = (*vB).h[AV_HINDEX(UIMM & 0x7)];
	for (i = 0; i < 8; i++)
	  (*vS).h[i] = h;
	PPC_INSN_VR(VS_BITMASK, VB_BITMASK);

0.4,6.VS,11.SIMM,16.0,21.780:VX:av:vspltisb %VD, %SIMM:Vector Splat Immediate Signed Byte
	int i;
	signed8 b = SIMM;
	/* manual 5-bit signed extension */
	if (b & 0x10)
	  b -= 0x20;
	for (i = 0; i < 16; i++)
	  (*vS).b[i] = b;
	PPC_INSN_VR(VS_BITMASK, 0);

0.4,6.VS,11.SIMM,16.0,21.844:VX:av:vspltish %VD, %SIMM:Vector Splat Immediate Signed Half Word
	int i;
	signed16 h = SIMM;
	/* manual 5-bit signed extension */
	if (h & 0x10)
	  h -= 0x20;
	for (i = 0; i < 8; i++)
	  (*vS).h[i] = h;
	PPC_INSN_VR(VS_BITMASK, 0);

0.4,6.VS,11.SIMM,16.0,21.908:VX:av:vspltisw %VD, %SIMM:Vector Splat Immediate Signed Word
	int i;
	signed32 w = SIMM;
	/* manual 5-bit signed extension */
	if (w & 0x10)
	  w -= 0x20;
	for (i = 0; i < 4; i++)
	  (*vS).w[i] = w;
	PPC_INSN_VR(VS_BITMASK, 0);

0.4,6.VS,11.UIMM,16.VB,21.652:VX:av:vspltw %VD, %VB, %UIMM:Vector Splat Word
	int i;
	unsigned32 w;
	w = (*vB).w[UIMM & 0x3];
	for (i = 0; i < 4; i++)
	  (*vS).w[i] = w;
	PPC_INSN_VR(VS_BITMASK, VB_BITMASK);


#
# Vector Shift Right instructions, 6-146 ... 6-154
#

0.4,6.VS,11.VA,16.VB,21.708:VX:av:vsr %VD, %VA, %VB:Vector Shift Right
	int sh, i, j, carry, new_carry;
	sh = (*vB).b[0] & 7;	/* don't bother checking everything */
	carry = 0;
	for (j = 0; j < 4; j++) {
	  if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
	    i = j;
	  else
	    i = (j + 2) % 4;
	  new_carry = (*vA).w[i] << (32 - sh);
	  (*vS).w[i] = ((*vA).w[i] >> sh) | carry;
	  carry = new_carry;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.772:VX:av:vsrab %VD, %VA, %VB:Vector Shift Right Algebraic Byte
	int i, sh;
	signed16 a;
	for (i = 0; i < 16; i++) {
	  sh = ((*vB).b[i]) & 7;
	  a = (signed16)(signed8)(*vA).b[i];
	  (*vS).b[i] = (a >> sh) & 0xff;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.836:VX:av:vsrah %VD, %VA, %VB:Vector Shift Right Algebraic Half Word
	int i, sh;
	signed32 a;
	for (i = 0; i < 8; i++) {
	  sh = ((*vB).h[i]) & 0xf;
	  a = (signed32)(signed16)(*vA).h[i];
	  (*vS).h[i] = (a >> sh) & 0xffff;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.900:VX:av:vsraw %VD, %VA, %VB:Vector Shift Right Algebraic Word
	int i, sh;
	signed64 a;
	for (i = 0; i < 4; i++) {
	  sh = ((*vB).w[i]) & 0xf;
	  a = (signed64)(signed32)(*vA).w[i];
	  (*vS).w[i] = (a >> sh) & 0xffffffff;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.516:VX:av:vsrb %VD, %VA, %VB:Vector Shift Right Byte
	int i, sh;
	for (i = 0; i < 16; i++) {
	  sh = ((*vB).b[i]) & 7;
	  (*vS).b[i] = (*vA).b[i] >> sh;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.580:VX:av:vsrh %VD, %VA, %VB:Vector Shift Right Half Word
	int i, sh;
	for (i = 0; i < 8; i++) {
	  sh = ((*vB).h[i]) & 0xf;
	  (*vS).h[i] = (*vA).h[i] >> sh;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.1100:VX:av:vsro %VD, %VA, %VB:Vector Shift Right Octet
	int i, sh;
	if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
	  sh = ((*vB).b[AV_BINDEX(15)] >> 3) & 0xf;
	else
	  sh = ((*vB).b[AV_BINDEX(0)] >> 3) & 0xf;
	for (i = 0; i < 16; i++) {
	  if (i < sh)
	    (*vS).b[AV_BINDEX(i)] = 0;
	  else
	    (*vS).b[AV_BINDEX(i)] = (*vA).b[AV_BINDEX(i - sh)];
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.644:VX:av:vsrw %VD, %VA, %VB:Vector Shift Right Word
	int i, sh;
	for (i = 0; i < 4; i++) {
	  sh = ((*vB).w[i]) & 0x1f;
	  (*vS).w[i] = (*vA).w[i] >> sh;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);


#
# Vector Subtract instructions, 6-155 ... 6-165
#

0.4,6.VS,11.VA,16.VB,21.1408:VX:av:vsubcuw %VD, %VA, %VB:Vector Subtract Carryout Unsigned Word
	int i;
	signed64 temp, a, b;
	for (i = 0; i < 4; i++) {
	  a = (signed64)(unsigned32)(*vA).w[i];
	  b = (signed64)(unsigned32)(*vB).w[i];
	  temp = a - b;
	  (*vS).w[i] = ~(temp >> 32) & 1;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.74:VX:av:vsubfp %VD, %VA, %VB:Vector Subtract Floating Point
	int i;
	unsigned32 f;
	sim_fpu a, b, d;
	for (i = 0; i < 4; i++) {
	  sim_fpu_32to (&a, (*vA).w[i]);
	  sim_fpu_32to (&b, (*vB).w[i]);
	  sim_fpu_sub (&d, &a, &b);
	  sim_fpu_to32 (&f, &d);
	  (*vS).w[i] = f;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.1792:VX:av:vsubsbs %VD, %VA, %VB:Vector Subtract Signed Byte Saturate
	int i, sat, tempsat;
	signed16 temp;
	sat = 0;
	for (i = 0; i < 16; i++) {
	  temp = (signed16)(signed8)(*vA).b[i] - (signed16)(signed8)(*vB).b[i];
	  (*vS).b[i] = altivec_signed_saturate_8(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.1856:VX:av:vsubshs %VD, %VA, %VB:Vector Subtract Signed Half Word Saturate
	int i, sat, tempsat;
	signed32 temp;
	sat = 0;
	for (i = 0; i < 8; i++) {
	  temp = (signed32)(signed16)(*vA).h[i] - (signed32)(signed16)(*vB).h[i];
	  (*vS).h[i] = altivec_signed_saturate_16(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.1920:VX:av:vsubsws %VD, %VA, %VB:Vector Subtract Signed Word Saturate
	int i, sat, tempsat;
	signed64 temp;
	sat = 0;
	for (i = 0; i < 4; i++) {
	  temp = (signed64)(signed32)(*vA).w[i] - (signed64)(signed32)(*vB).w[i];
	  (*vS).w[i] = altivec_signed_saturate_32(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.1024:VX:av:vsububm %VD, %VA, %VB:Vector Subtract Unsigned Byte Modulo
	int i;
	for (i = 0; i < 16; i++)
	  (*vS).b[i] = (*vA).b[i] - (*vB).b[i];
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.1536:VX:av:vsububs %VD, %VA, %VB:Vector Subtract Unsigned Byte Saturate
	int i, sat, tempsat;
	signed16 temp;
	sat = 0;
	for (i = 0; i < 16; i++) {
	  temp = (signed16)(unsigned8)(*vA).b[i] - (signed16)(unsigned8)(*vB).b[i];
	  (*vS).b[i] = altivec_unsigned_saturate_8(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.1088:VX:av:vsubuhm %VD, %VA, %VB:Vector Subtract Unsigned Half Word Modulo
	int i;
	for (i = 0; i < 8; i++)
	  (*vS).h[i] = ((*vA).h[i] - (*vB).h[i]) & 0xffff;
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.1600:VX:av:vsubuhs %VD, %VA, %VB:Vector Subtract Unsigned Half Word Saturate
	int i, sat, tempsat;
	signed32 temp;
	for (i = 0; i < 8; i++) {
	  temp = (signed32)(unsigned16)(*vA).h[i] - (signed32)(unsigned16)(*vB).h[i];
	  (*vS).h[i] = altivec_unsigned_saturate_16(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.1152:VX:av:vsubuwm %VD, %VA, %VB:Vector Subtract Unsigned Word Modulo
	int i;
	for (i = 0; i < 4; i++)
	  (*vS).w[i] = (*vA).w[i] - (*vB).w[i];
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.1664:VX:av:vsubuws %VD, %VA, %VB:Vector Subtract Unsigned Word Saturate
	int i, sat, tempsat;
	signed64 temp;
	for (i = 0; i < 4; i++) {
	  temp = (signed64)(unsigned32)(*vA).w[i] - (signed64)(unsigned32)(*vB).w[i];
	  (*vS).w[i] = altivec_unsigned_saturate_32(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK);


#
# Vector Sum instructions, 6-166 ... 6-170
#

0.4,6.VS,11.VA,16.VB,21.1928:VX:av:vsumsws %VD, %VA, %VB:Vector Sum Across Signed Word Saturate
	int i, sat;
	signed64 temp;
	temp = (signed64)(signed32)(*vB).w[3];
	for (i = 0; i < 4; i++)
	  temp += (signed64)(signed32)(*vA).w[i];
	(*vS).w[3] = altivec_signed_saturate_32(temp, &sat);
	(*vS).w[0] = (*vS).w[1] = (*vS).w[2] = 0;
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.1672:VX:av:vsum2sws %VD, %VA, %VB:Vector Sum Across Partial (1/2) Signed Word Saturate
	int i, j, sat, tempsat;
	signed64 temp;
	for (j = 0; j < 4; j += 2) {
	  temp = (signed64)(signed32)(*vB).w[j+1];
	  temp += (signed64)(signed32)(*vA).w[j] + (signed64)(signed32)(*vA).w[j+1];
	  (*vS).w[j+1] = altivec_signed_saturate_32(temp, &tempsat);
	  sat |= tempsat;
	}
	(*vS).w[0] = (*vS).w[2] = 0;
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.1800:VX:av:vsum4sbs %VD, %VA, %VB:Vector Sum Across Parti