altivec.igen

gdb-6.0 linux 下的调试工具

	for (i = 0; i < 16; i += 2) {
	  (*vS).b[AV_BINDEX(i)] = (*vA).b[AV_BINDEX((i/2) + 8)];
	  (*vS).b[AV_BINDEX(i+1)] = (*vB).b[AV_BINDEX((i/2) + 8)]; 
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.332:VX:av:vmrglh %VD, %VA, %VB:Vector Merge Low Half Word
	int i;
	for (i = 0; i < 8; i += 2) {
	  (*vS).h[AV_HINDEX(i)] = (*vA).h[AV_HINDEX((i/2) + 4)];
	  (*vS).h[AV_HINDEX(i+1)] = (*vB).h[AV_HINDEX((i/2) + 4)]; 
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.396:VX:av:vmrglw %VD, %VA, %VB:Vector Merge Low Word
	int i;
	for (i = 0; i < 4; i += 2) {
	  (*vS).w[i] = (*vA).w[(i/2) + 2];
	  (*vS).w[i+1] = (*vB).w[(i/2) + 2]; 
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);


#
# Vector Multiply Sum instructions, 6-95 ... 6-100
#

0.4,6.VS,11.VA,16.VB,21.VC,26.37:VAX:av:vmsummbm %VD, %VA, %VB, %VC:Vector Multiply Sum Mixed-Sign Byte Modulo
	int i, j;
	signed32 temp;
	signed16 prod, a;
	unsigned16 b;
	for (i = 0; i < 4; i++) {
	  temp = (*vC).w[i];
	  for (j = 0; j < 4; j++) {
	    a = (signed16)(signed8)(*vA).b[i*4+j]; 
	    b = (*vB).b[i*4+j];
	    prod = a * b;
	    temp += (signed32)prod;
	  }
	  (*vS).w[i] = temp;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK);

0.4,6.VS,11.VA,16.VB,21.VC,26.40:VAX:av:vmsumshm %VD, %VA, %VB, %VC:Vector Multiply Sum Signed Half Word Modulo
	int i, j;
	signed32 temp, prod, a, b;
	for (i = 0; i < 4; i++) {
	  temp = (*vC).w[i];
	  for (j = 0; j < 2; j++) {
	    a = (signed32)(signed16)(*vA).h[i*2+j]; 
	    b = (signed32)(signed16)(*vB).h[i*2+j];
	    prod = a * b;
	    temp += prod;
	  }
	  (*vS).w[i] = temp;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK);

0.4,6.VS,11.VA,16.VB,21.VC,26.41:VAX:av:vmsumshs %VD, %VA, %VB, %VC:Vector Multiply Sum Signed Half Word Saturate
	int i, j, sat, tempsat;
	signed64 temp;
	signed32 prod, a, b;
	sat = 0;
	for (i = 0; i < 4; i++) {
	  temp = (signed64)(signed32)(*vC).w[i];
	  for (j = 0; j < 2; j++) {
	    a = (signed32)(signed16)(*vA).h[i*2+j]; 
	    b = (signed32)(signed16)(*vB).h[i*2+j];
	    prod = a * b;
	    temp += (signed64)prod;
	  }
	  (*vS).w[i] = altivec_signed_saturate_32(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK);

0.4,6.VS,11.VA,16.VB,21.VC,26.36:VAX:av:vmsumubm %VD, %VA, %VB, %VC:Vector Multiply Sum Unsigned Byte Modulo
	int i, j;
	unsigned32 temp;
	unsigned16 prod, a, b;
	for (i = 0; i < 4; i++) {
	  temp = (*vC).w[i];
	  for (j = 0; j < 4; j++) {
	    a = (*vA).b[i*4+j]; 
	    b = (*vB).b[i*4+j];
	    prod = a * b;
	    temp += prod;
	  }
	  (*vS).w[i] = temp;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK);

0.4,6.VS,11.VA,16.VB,21.VC,26.38:VAX:av:vmsumuhm %VD, %VA, %VB, %VC:Vector Multiply Sum Unsigned Half Word Modulo
	int i, j;
	unsigned32 temp, prod, a, b;
	for (i = 0; i < 4; i++) {
	  temp = (*vC).w[i];
	  for (j = 0; j < 2; j++) {
	    a = (*vA).h[i*2+j]; 
	    b = (*vB).h[i*2+j];
	    prod = a * b;
	    temp += prod;
	  }
	  (*vS).w[i] = temp;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK);

0.4,6.VS,11.VA,16.VB,21.VC,26.39:VAX:av:vmsumuhs %VD, %VA, %VB, %VC:Vector Multiply Sum Unsigned Half Word Saturate
	int i, j, sat, tempsat;
	unsigned32 temp, prod, a, b;
	sat = 0;
	for (i = 0; i < 4; i++) {
	  temp = (*vC).w[i];
	  for (j = 0; j < 2; j++) {
	    a = (*vA).h[i*2+j]; 
	    b = (*vB).h[i*2+j];
	    prod = a * b;
	    temp += prod;
	  }
	  (*vS).w[i] = altivec_unsigned_saturate_32(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK);


#
# Vector Multiply Even/Odd instructions, 6-101 ... 6-108
#

0.4,6.VS,11.VA,16.VB,21.776:VX:av:vmulesb %VD, %VA, %VB:Vector Multiply Even Signed Byte
	int i;
	signed8 a, b;
	signed16 prod;
	for (i = 0; i < 8; i++) {
	  a = (*vA).b[AV_BINDEX(i*2)]; 
	  b = (*vB).b[AV_BINDEX(i*2)];
	  prod = a * b;
	  (*vS).h[AV_HINDEX(i)] = prod;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.840:VX:av:vmulesh %VD, %VA, %VB:Vector Multiply Even Signed Half Word
	int i;
	signed16 a, b;
	signed32 prod;
	for (i = 0; i < 4; i++) {
	  a = (*vA).h[AV_HINDEX(i*2)]; 
	  b = (*vB).h[AV_HINDEX(i*2)];
	  prod = a * b;
	  (*vS).w[i] = prod;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.520:VX:av:vmuleub %VD, %VA, %VB:Vector Multiply Even Unsigned Byte
	int i;
	unsigned8 a, b;
	unsigned16 prod;
	for (i = 0; i < 8; i++) {
	  a = (*vA).b[AV_BINDEX(i*2)]; 
	  b = (*vB).b[AV_BINDEX(i*2)];
	  prod = a * b;
	  (*vS).h[AV_HINDEX(i)] = prod;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.584:VX:av:vmuleuh %VD, %VA, %VB:Vector Multiply Even Unsigned Half Word
	int i;
	unsigned16 a, b;
	unsigned32 prod;
	for (i = 0; i < 4; i++) {
	  a = (*vA).h[AV_HINDEX(i*2)]; 
	  b = (*vB).h[AV_HINDEX(i*2)];
	  prod = a * b;
	  (*vS).w[i] = prod;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.264:VX:av:vmulosb %VD, %VA, %VB:Vector Multiply Odd Signed Byte
	int i;
	signed8 a, b;
	signed16 prod;
	for (i = 0; i < 8; i++) {
	  a = (*vA).b[AV_BINDEX((i*2)+1)]; 
	  b = (*vB).b[AV_BINDEX((i*2)+1)];
	  prod = a * b;
	  (*vS).h[AV_HINDEX(i)] = prod;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.328:VX:av:vmulosh %VD, %VA, %VB:Vector Multiply Odd Signed Half Word
	int i;
	signed16 a, b;
	signed32 prod;
	for (i = 0; i < 4; i++) {
	  a = (*vA).h[AV_HINDEX((i*2)+1)]; 
	  b = (*vB).h[AV_HINDEX((i*2)+1)];
	  prod = a * b;
	  (*vS).w[i] = prod;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.8:VX:av:vmuloub %VD, %VA, %VB:Vector Multiply Odd Unsigned Byte
	int i;
	unsigned8 a, b;
	unsigned16 prod;
	for (i = 0; i < 8; i++) {
	  a = (*vA).b[AV_BINDEX((i*2)+1)]; 
	  b = (*vB).b[AV_BINDEX((i*2)+1)];
	  prod = a * b;
	  (*vS).h[AV_HINDEX(i)] = prod;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.72:VX:av:vmulouh %VD, %VA, %VB:Vector Multiply Odd Unsigned Half Word
	int i;
	unsigned16 a, b;
	unsigned32 prod;
	for (i = 0; i < 4; i++) {
	  a = (*vA).h[AV_HINDEX((i*2)+1)]; 
	  b = (*vB).h[AV_HINDEX((i*2)+1)];
	  prod = a * b;
	  (*vS).w[i] = prod;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);


#
# Vector Negative Multiply-Subtract instruction, 6-109
#

0.4,6.VS,11.VA,16.VB,21.VC,26.47:VX:av:vnmsubfp %VD, %VA, %VB, %VC:Vector Negative Multiply-Subtract Floating Point
	int i;
	unsigned32 f;
	sim_fpu a, b, c, d, i1, i2;
	for (i = 0; i < 4; i++) {
	  sim_fpu_32to (&a, (*vA).w[i]);
	  sim_fpu_32to (&b, (*vB).w[i]);
	  sim_fpu_32to (&c, (*vC).w[i]);
	  sim_fpu_mul (&i1, &a, &c);
	  sim_fpu_sub (&i2, &i1, &b);
	  sim_fpu_neg (&d, &i2);
	  sim_fpu_to32 (&f, &d);
	  (*vS).w[i] = f;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK);


#
# Vector Logical OR instructions, 6-110, 6-111, 6-177
#

0.4,6.VS,11.VA,16.VB,21.1284:VX:av:vnor %VD, %VA, %VB:Vector Logical NOR
	int i;
	for (i = 0; i < 4; i++)
	  (*vS).w[i] = ~((*vA).w[i] | (*vB).w[i]);
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.1156:VX:av:vor %VD, %VA, %VB:Vector Logical OR
	int i;
	for (i = 0; i < 4; i++)
	  (*vS).w[i] = (*vA).w[i] | (*vB).w[i];
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.1220:VX:av:vxor %VD, %VA, %VB:Vector Logical XOR
	int i;
	for (i = 0; i < 4; i++)
	  (*vS).w[i] = (*vA).w[i] ^ (*vB).w[i];
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);


#
# Vector Permute instruction, 6-112
#

0.4,6.VS,11.VA,16.VB,21.VC,26.43:VX:av:vperm %VD, %VA, %VB, %VC:Vector Permute
	int i, who;
	for (i = 0; i < 16; i++) {
	  who = (*vC).b[AV_BINDEX(i)] & 0x1f;
	  if (who & 0x10)
	    (*vS).b[AV_BINDEX(i)] = (*vB).b[AV_BINDEX(who & 0xf)];
	  else
	    (*vS).b[AV_BINDEX(i)] = (*vA).b[AV_BINDEX(who & 0xf)];
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK);


#
# Vector Pack instructions, 6-113 ... 6-121
#

0.4,6.VS,11.VA,16.VB,21.782:VX:av:vpkpx %VD, %VA, %VB:Vector Pack Pixel32
	int i;
	for (i = 0; i < 4; i++) {
	  (*vS).h[AV_HINDEX(i+4)] = ((((*vB).w[i]) >> 9) & 0xfc00)
	               | ((((*vB).w[i]) >> 6) & 0x03e0)
	               | ((((*vB).w[i]) >> 3) & 0x001f);
	  (*vS).h[AV_HINDEX(i)] = ((((*vA).w[i]) >> 9) & 0xfc00)
	             | ((((*vA).w[i]) >> 6) & 0x03e0)
	             | ((((*vA).w[i]) >> 3) & 0x001f);
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.398:VX:av:vpkshss %VD, %VA, %VB:Vector Pack Signed Half Word Signed Saturate
	int i, sat, tempsat;
	signed16 temp;
	sat = 0;
	for (i = 0; i < 16; i++) {
	  if (i < 8)
	    temp = (*vA).h[AV_HINDEX(i)];
	  else
	    temp = (*vB).h[AV_HINDEX(i-8)];
	  (*vS).b[AV_BINDEX(i)] = altivec_signed_saturate_8(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.270:VX:av:vpkshus %VD, %VA, %VB:Vector Pack Signed Half Word Unsigned Saturate
	int i, sat, tempsat;
	signed16 temp;
	sat = 0;
	for (i = 0; i < 16; i++) {
	  if (i < 8)
	    temp = (*vA).h[AV_HINDEX(i)];
	  else
	    temp = (*vB).h[AV_HINDEX(i-8)];
	  (*vS).b[AV_BINDEX(i)] = altivec_unsigned_saturate_8(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.462:VX:av:vpkswss %VD, %VA, %VB:Vector Pack Signed Word Signed Saturate
	int i, sat, tempsat;
	signed32 temp;
	sat = 0;
	for (i = 0; i < 8; i++) {
	  if (i < 4)
	    temp = (*vA).w[i];
	  else
	    temp = (*vB).w[i-4];
	  (*vS).h[AV_HINDEX(i)] = altivec_signed_saturate_16(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.334:VX:av:vpkswus %VD, %VA, %VB:Vector Pack Signed Word Unsigned Saturate
	int i, sat, tempsat;
	signed32 temp;
	sat = 0;
	for (i = 0; i < 8; i++) {
	  if (i < 4)
	    temp = (*vA).w[i];
	  else
	    temp = (*vB).w[i-4];
	  (*vS).h[AV_HINDEX(i)] = altivec_unsigned_saturate_16(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.14:VX:av:vpkuhum %VD, %VA, %VB:Vector Pack Unsigned Half Word Unsigned Modulo
	int i;
	for (i = 0; i < 16; i++)
	  if (i < 8)
	    (*vS).b[AV_BINDEX(i)] = (*vA).h[AV_HINDEX(i)];
	  else
	    (*vS).b[AV_BINDEX(i)] = (*vB).h[AV_HINDEX(i-8)];
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.142:VX:av:vpkuhus %VD, %VA, %VB:Vector Pack Unsigned Half Word Unsigned Saturate
	int i, sat, tempsat;
	signed16 temp;
	sat = 0;
	for (i = 0; i < 16; i++) {
	  if (i < 8)
	    temp = (*vA).h[AV_HINDEX(i)];
	  else
	    temp = (*vB).h[AV_HINDEX(i-8)];
	  /* force positive in signed16, ok as we'll toss the bit away anyway */
	  temp &= ~0x8000;
	  (*vS).b[AV_BINDEX(i)] = altivec_unsigned_saturate_8(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.78:VX:av:vpkuwum %VD, %VA, %VB:Vector Pack Unsigned Word Unsigned Modulo
	int i;
	for (i = 0; i < 8; i++)
	  if (i < 8)
	    (*vS).h[AV_HINDEX(i)] = (*vA).w[i];
	  else
	    (*vS).h[AV_HINDEX(i)] = (*vB).w[i-8];
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.206:VX:av:vpkuwus %VD, %VA, %VB:Vector Pack Unsigned Word Unsigned Saturate
	int i, sat, tempsat;
	signed32 temp;
	sat = 0;
	for (i = 0; i < 8; i++) {
	  if (i < 4)
	    temp = (*vA).w[i];
	  else
	    temp = (*vB).w[i-4];
	  /* force positive in signed32, ok as we'll toss the bit away anyway */
	  temp &= ~0x80000000;
	  (*vS).h[AV_HINDEX(i)] = altivec_unsigned_saturate_16(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK);


#
# Vector Reciprocal instructions, 6-122, 6-123, 6-131
#

0.4,6.VS,11.0,16.VB,21.266:VX:av:vrefp %VD, %VB:Vector Reciprocal Estimate Floating Point
	int i;
	unsigned32 f;
	sim_fpu op, d;
	for (i = 0; i < 4; i++) {
	  sim_fpu_32to (&op, (*vB).w[i]);
	  sim_fpu_div (&d, &sim_fpu_one, &op);
	  sim_fpu_to32 (&f, &d);
	  (*vS).w[i] = f;
	}
	PPC_INSN_VR(VS_BITMASK, VB_BITMASK);

0.4,6.VS,11.0,16.VB,21.330:VX:av:vrsqrtefp %VD, %VB:Vector Reciprocal Square Root Estimate Floating Point
	int i;
	unsigned32 f;
	sim_fpu op, i1, one, d;
	for (i = 0; i < 4; i++) {
	  sim_fpu_32to (&op, (*vB).w[i]);
	  sim_fpu_sqrt (&i1, &op);
	  sim_fpu_div (&d, &sim_fpu_one, &i1);
	  sim_fpu_to32 (&f, &d);
	  (*vS).w[i] = f;
	}
	PPC_INSN_VR(VS_BITMASK, VB_BITMASK);


#
# Vector Round instructions, 6-124 ... 6-127
#

0.4,6.VS,11.0,16.VB,21.714:VX:av:vrfim %VD, %VB:Vector Round to Floating-Point Integer towards Minus Infinity