altivec.igen

gdb-6.0 linux 下的调试工具

0.31,6.VS,11.RA,16.RB,21.359,31.0:X:av:lvxl %VD, %RA, %RB:Load Vector Indexed LRU
	unsigned_word b;
	unsigned_word EA;
	if (RA_is_0) b = 0;
	else         b = *rA;
	EA = (b + *rB) & ~0xf;
	if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) {
	  (*vS).w[0] = MEM(unsigned, EA + 0, 4);
	  (*vS).w[1] = MEM(unsigned, EA + 4, 4);
	  (*vS).w[2] = MEM(unsigned, EA + 8, 4);
	  (*vS).w[3] = MEM(unsigned, EA + 12, 4);
	} else {
	  (*vS).w[0] = MEM(unsigned, EA + 12, 4);
	  (*vS).w[1] = MEM(unsigned, EA + 8, 4);
	  (*vS).w[2] = MEM(unsigned, EA + 4, 4);
	  (*vS).w[3] = MEM(unsigned, EA + 0, 4);
	}
	PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0);

#
# Move to/from VSCR instructions, 6-23 & 6-24.
#

0.4,6.VS,11.0,16.0,21.1540:VX:av:mfvscr %VS:Move from Vector Status and Control Register
	(*vS).w[0] = 0;
	(*vS).w[1] = 0;
	(*vS).w[2] = 0;
	(*vS).w[3] = VSCR;
	PPC_INSN_FROM_VSCR(VS_BITMASK);

0.4,6.0,11.0,16.VB,21.1604:VX:av:mtvscr %VB:Move to Vector Status and Control Register
	VSCR = (*vB).w[3];
	PPC_INSN_TO_VSCR(VB_BITMASK);

#
# Store instructions, 6-25 ... 6-29.
#

0.31,6.VS,11.RA,16.RB,21.135,31.0:X:av:stvebx %VD, %RA, %RB:Store Vector Element Byte Indexed
	unsigned_word b;
	unsigned_word EA;
	unsigned_word eb;
	if (RA_is_0) b = 0;
	else         b = *rA;
	EA = b + *rB;
	eb = EA & 0xf;
	if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
	  STORE(EA, 1, (*vS).b[eb]);
	else
	  STORE(EA, 1, (*vS).b[15-eb]);
	PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0);

0.31,6.VS,11.RA,16.RB,21.167,31.0:X:av:stvehx %VD, %RA, %RB:Store Vector Element Half Word Indexed
	unsigned_word b;
	unsigned_word EA;
	unsigned_word eb;
	if (RA_is_0) b = 0;
	else         b = *rA;
	EA = (b + *rB) & ~1;
	eb = EA & 0xf;
	if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
	  STORE(EA, 2, (*vS).h[eb/2]);
	else
	  STORE(EA, 2, (*vS).h[7-eb]);
	PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0);

0.31,6.VS,11.RA,16.RB,21.199,31.0:X:av:stvewx %VD, %RA, %RB:Store Vector Element Word Indexed
	unsigned_word b;
	unsigned_word EA;
	unsigned_word eb;
	if (RA_is_0) b = 0;
	else         b = *rA;
	EA = (b + *rB) & ~3;
	eb = EA & 0xf;
	if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
	  STORE(EA, 4, (*vS).w[eb/4]);
	else
	  STORE(EA, 4, (*vS).w[3-(eb/4)]);
	PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0);

0.31,6.VS,11.RA,16.RB,21.231,31.0:X:av:stvx %VD, %RA, %RB:Store Vector Indexed
	unsigned_word b;
	unsigned_word EA;
	if (RA_is_0) b = 0;
	else         b = *rA;
	EA = (b + *rB) & ~0xf;
	if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) {
	  STORE(EA + 0, 4, (*vS).w[0]);
	  STORE(EA + 4, 4, (*vS).w[1]);
	  STORE(EA + 8, 4, (*vS).w[2]);
	  STORE(EA + 12, 4, (*vS).w[3]);
	} else {
	  STORE(EA + 12, 4, (*vS).w[0]);
	  STORE(EA + 8, 4, (*vS).w[1]);
	  STORE(EA + 4, 4, (*vS).w[2]);
	  STORE(EA + 0, 4, (*vS).w[3]);
	}
	PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0);

0.31,6.VS,11.RA,16.RB,21.487,31.0:X:av:stvxl %VD, %RA, %RB:Store Vector Indexed LRU
	unsigned_word b;
	unsigned_word EA;
	if (RA_is_0) b = 0;
	else         b = *rA;
	EA = (b + *rB) & ~0xf;
	if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) {
	  STORE(EA + 0, 4, (*vS).w[0]);
	  STORE(EA + 4, 4, (*vS).w[1]);
	  STORE(EA + 8, 4, (*vS).w[2]);
	  STORE(EA + 12, 4, (*vS).w[3]);
	} else {
	  STORE(EA + 12, 4, (*vS).w[0]);
	  STORE(EA + 8, 4, (*vS).w[1]);
	  STORE(EA + 4, 4, (*vS).w[2]);
	  STORE(EA + 0, 4, (*vS).w[3]);
	}
	PPC_INSN_INT_VR(0, RA_BITMASK | RB_BITMASK, VS_BITMASK, 0);

#
# Vector Add instructions, 6-30 ... 6-40.
#

0.4,6.VS,11.VA,16.VB,21.384:VX:av:vaddcuw %VD, %VA, %VB:Vector Add Carryout Unsigned Word
	unsigned64 temp;
	int i;
	for (i = 0; i < 4; i++) {
	  temp = (unsigned64)(*vA).w[i] + (unsigned64)(*vB).w[i];
	  (*vS).w[i] = temp >> 32;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.10:VX:av:vaddfp %VD, %VA, %VB:Vector Add Floating Point
	int i;
	unsigned32 f;
	sim_fpu a, b, d;
	for (i = 0; i < 4; i++) {
	  sim_fpu_32to (&a, (*vA).w[i]);
	  sim_fpu_32to (&b, (*vB).w[i]);
	  sim_fpu_add (&d, &a, &b);
	  sim_fpu_to32 (&f, &d);
	  (*vS).w[i] = f;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);
	
0.4,6.VS,11.VA,16.VB,21.768:VX:av:vaddsbs %VD, %VA, %VB:Vector Add Signed Byte Saturate
	int i, sat, tempsat;
	signed16 temp;
	for (i = 0; i < 16; i++) {
	  temp = (signed16)(signed8)(*vA).b[i] + (signed16)(signed8)(*vB).b[i];
	  (*vS).b[i] = altivec_signed_saturate_8(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.832:VX:av:vaddshs %VD, %VA, %VB:Vector Add Signed Half Word Saturate
	int i, sat, tempsat;
	signed32 temp, a, b;
	for (i = 0; i < 8; i++) {
	  a = (signed32)(signed16)(*vA).h[i];
	  b = (signed32)(signed16)(*vB).h[i];
	  temp = a + b;
	  (*vS).h[i] = altivec_signed_saturate_16(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.896:VX:av:vaddsws %VD, %VA, %VB:Vector Add Signed Word Saturate
	int i, sat, tempsat;
	signed64 temp;
	for (i = 0; i < 4; i++) {
	  temp = (signed64)(signed32)(*vA).w[i] + (signed64)(signed32)(*vB).w[i];
	  (*vS).w[i] = altivec_signed_saturate_32(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.0:VX:av:vaddubm %VD, %VA, %VB:Vector Add Unsigned Byte Modulo
	int i;
	for (i = 0; i < 16; i++)
	  (*vS).b[i] = ((*vA).b[i] + (*vB).b[i]) & 0xff;
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.512:VX:av:vaddubs %VD, %VA, %VB:Vector Add Unsigned Byte Saturate
	int i, sat, tempsat;
	signed16 temp;
	sat = 0;
	for (i = 0; i < 16; i++) {
	  temp = (signed16)(unsigned8)(*vA).b[i] + (signed16)(unsigned8)(*vB).b[i];
	  (*vS).b[i] = altivec_unsigned_saturate_8(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.64:VX:av:vadduhm %VD, %VA, %VB:Vector Add Unsigned Half Word Modulo
	int i;
	for (i = 0; i < 8; i++)
	  (*vS).h[i] = ((*vA).h[i] + (*vB).h[i]) & 0xffff;
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.576:VX:av:vadduhs %VD, %VA, %VB:Vector Add Unsigned Half Word Saturate
	int i, sat, tempsat;
	signed32 temp;
	for (i = 0; i < 8; i++) {
	  temp = (signed32)(unsigned16)(*vA).h[i] + (signed32)(unsigned16)(*vB).h[i];
	  (*vS).h[i] = altivec_unsigned_saturate_16(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.128:VX:av:vadduwm %VD, %VA, %VB:Vector Add Unsigned Word Modulo
	int i;
	for (i = 0; i < 4; i++)
	  (*vS).w[i] = (*vA).w[i] + (*vB).w[i];
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.640:VX:av:vadduws %VD, %VA, %VB:Vector Add Unsigned Word Saturate
	int i, sat, tempsat;
	signed64 temp;
	for (i = 0; i < 4; i++) {
	  temp = (signed64)(unsigned32)(*vA).w[i] + (signed64)(unsigned32)(*vB).w[i];
	  (*vS).w[i] = altivec_unsigned_saturate_32(temp, &tempsat);
	  sat |= tempsat;
	}
	ALTIVEC_SET_SAT(sat);
	PPC_INSN_VR_VSCR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

#
# Vector AND instructions, 6-41, 6-42
#

0.4,6.VS,11.VA,16.VB,21.1028:VX:av:vand %VD, %VA, %VB:Vector Logical AND
	int i;
	for (i = 0; i < 4; i++)
	  (*vS).w[i] = (*vA).w[i] & (*vB).w[i];
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.1092:VX:av:vandc %VD, %VA, %VB:Vector Logical AND with Compliment
	int i;
	for (i = 0; i < 4; i++)
	  (*vS).w[i] = (*vA).w[i] & ~((*vB).w[i]);
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);


#
# Vector Average instructions, 6-43, 6-48
#

0.4,6.VS,11.VA,16.VB,21.1282:VX:av:vavgsb %VD, %VA, %VB:Vector Average Signed Byte
	int i;
	signed16 temp, a, b;
	for (i = 0; i < 16; i++) {
	  a = (signed16)(signed8)(*vA).b[i];
	  b = (signed16)(signed8)(*vB).b[i];
	  temp = a + b + 1;
	  (*vS).b[i] = (temp >> 1) & 0xff;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.1346:VX:av:vavgsh %VD, %VA, %VB:Vector Average Signed Half Word
	int i;
	signed32 temp, a, b;
	for (i = 0; i < 8; i++) {
	  a = (signed32)(signed16)(*vA).h[i];
	  b = (signed32)(signed16)(*vB).h[i];
	  temp = a + b + 1;
	  (*vS).h[i] = (temp >> 1) & 0xffff;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.1410:VX:av:vavgsw %VD, %VA, %VB:Vector Average Signed Word
	int i;
	signed64 temp, a, b;
	for (i = 0; i < 4; i++) {
	  a = (signed64)(signed32)(*vA).w[i];
	  b = (signed64)(signed32)(*vB).w[i];
	  temp = a + b + 1;
	  (*vS).w[i] = (temp >> 1) & 0xffffffff;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.1026:VX:av:vavgub %VD, %VA, %VB:Vector Average Unsigned Byte
	int i;
	unsigned16 temp, a, b;
	for (i = 0; i < 16; i++) {
	  a = (*vA).b[i];
	  b = (*vB).b[i];
	  temp = a + b + 1;
	  (*vS).b[i] = (temp >> 1) & 0xff;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.1090:VX:av:vavguh %VD, %VA, %VB:Vector Average Unsigned Half Word
	int i;
	unsigned32 temp, a, b;
	for (i = 0; i < 8; i++) {
	  a = (*vA).h[i];
	  b = (*vB).h[i];
	  temp = a + b + 1;
	  (*vS).h[i] = (temp >> 1) & 0xffff;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

0.4,6.VS,11.VA,16.VB,21.1154:VX:av:vavguw %VD, %VA, %VB:Vector Average Unsigned Word
	int i;
	unsigned64 temp, a, b;
	for (i = 0; i < 4; i++) {
	  a = (*vA).w[i];
	  b = (*vB).w[i];
	  temp = a + b + 1;
	  (*vS).w[i] = (temp >> 1) & 0xffffffff;
	}
	PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);

#
# Vector Fixed Point Convert instructions, 6-49, 6-50
#

0.4,6.VS,11.UIMM,16.VB,21.842:VX:av:vcfsx %VD, %VB, %UIMM:Vector Convert From Signed Fixed-Point Word
	int i;
	unsigned32 f;
	sim_fpu b, div, d;
	for (i = 0; i < 4; i++) {
	  sim_fpu_32to (&b, (*vB).w[i]);
	  sim_fpu_u32to (&div, 2 << UIMM, sim_fpu_round_default);
	  sim_fpu_div (&d, &b, &div);
	  sim_fpu_to32 (&f, &d);
	  (*vS).w[i] = f;
	}
	PPC_INSN_VR(VS_BITMASK, VB_BITMASK);

0.4,6.VS,11.UIMM,16.VB,21.778:VX:av:vcfux %VD, %VA, %UIMM:Vector Convert From Unsigned Fixed-Point Word
	int i;
	unsigned32 f;
	sim_fpu b, d, div;
	for (i = 0; i < 4; i++) {
	  sim_fpu_32to (&b, (*vB).w[i]);
	  sim_fpu_u32to (&div, 2 << UIMM, sim_fpu_round_default);
	  sim_fpu_div (&d, &b, &div);
	  sim_fpu_to32u (&f, &d, sim_fpu_round_default);
	  (*vS).w[i] = f;
	}
	PPC_INSN_VR(VS_BITMASK, VB_BITMASK);

#
# Vector Compare instructions, 6-51 ... 6-64
#

0.4,6.VS,11.VA,16.VB,21.RC,22.966:VXR:av:vcmpbpfpx %VD, %VA, %VB:Vector Compare Bounds Floating Point
	int i, le, ge;
	sim_fpu a, b, d;
	for (i = 0; i < 4; i++) {
	  sim_fpu_32to (&a, (*vA).w[i]);
	  sim_fpu_32to (&b, (*vB).w[i]);
	  le = sim_fpu_is_le(&a, &b);
	  ge = sim_fpu_is_ge(&a, &b);
	  (*vS).w[i] = (le ? 0 : 1 << 31) | (ge ? 0 : 1 << 30);
	}
	if (RC)
	  ALTIVEC_SET_CR6(vS, 0);
	PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0);

0.4,6.VS,11.VA,16.VB,21.RC,22.198:VXR:av:vcmpeqfpx %VD, %VA, %VB:Vector Compare Equal-to-Floating Point
	int i;
	sim_fpu a, b;
	for (i = 0; i < 4; i++) {
	  sim_fpu_32to (&a, (*vA).w[i]);
	  sim_fpu_32to (&b, (*vB).w[i]);
	  if (sim_fpu_is_eq(&a, &b))
	    (*vS).w[i] = 0xffffffff;
	  else
	    (*vS).w[i] = 0;
	}
	if (RC)
	  ALTIVEC_SET_CR6(vS, 1);
	PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0);

0.4,6.VS,11.VA,16.VB,21.RC,22.6:VXR:av:vcmpequbx %VD, %VA, %VB:Vector Compare Equal-to Unsigned Byte
	int i;
	for (i = 0; i < 16; i++)
	  if ((*vA).b[i] == (*vB).b[i])
	    (*vS).b[i] = 0xff;
	  else
	    (*vS).b[i] = 0;
	if (RC)
	  ALTIVEC_SET_CR6(vS, 1);
	PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0);

0.4,6.VS,11.VA,16.VB,21.RC,22.70:VXR:av:vcmpequhx %VD, %VA, %VB:Vector Compare Equal-to Unsigned Half Word
	int i;
	for (i = 0; i < 8; i++)
	  if ((*vA).h[i] == (*vB).h[i])
	    (*vS).h[i] = 0xffff;
	  else
	    (*vS).h[i] = 0;
	if (RC)
	  ALTIVEC_SET_CR6(vS, 1);
	PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0);

0.4,6.VS,11.VA,16.VB,21.RC,22.134:VXR:av:vcmpequwx %VD, %VA, %VB:Vector Compare Equal-to Unsigned Word
	int i;
	for (i = 0; i < 4; i++)
	  if ((*vA).w[i] == (*vB).w[i])
	    (*vS).w[i] = 0xffffffff;
	  else
	    (*vS).w[i] = 0;
	if (RC)
	  ALTIVEC_SET_CR6(vS, 1);
	PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0);

0.4,6.VS,11.VA,16.VB,21.RC,22.454:VXR:av:vcmpgefpx %VD, %VA, %VB:Vector Compare Greater-Than-or-Equal-to Floating Point
	int i;
	sim_fpu a, b;
	for (i = 0; i < 4; i++) {
	  sim_fpu_32to (&a, (*vA).w[i]);
	  sim_fpu_32to (&b, (*vB).w[i]);
	  if (sim_fpu_is_ge(&a, &b))
	    (*vS).w[i] = 0xffffffff;
	  else
	    (*vS).w[i] = 0;
	}
	if (RC)
	  ALTIVEC_SET_CR6(vS, 1);
	PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0);

0.4,6.VS,11.VA,16.VB,21.RC,22.710:VXR:av:vcmpgtfpx %VD, %VA, %VB:Vector Compare Greater-Than Floating Point
	int i;
	sim_fpu a, b;
	for (i = 0; i < 4; i++) {
	  sim_fpu_32to (&a, (*vA).w[i]);
	  sim_fpu_32to (&b, (*vB).w[i]);
	  if (sim_fpu_is_gt(&a, &b))
	    (*vS).w[i] = 0xffffffff;
	  else
	    (*vS).w[i] = 0;
	}
	if (RC)
	  ALTIVEC_SET_CR6(vS, 1);
	PPC_INSN_VR_CR(VS_BITMASK, VA_BITMASK | VB_BITMASK, RC ? 0x000000f0 : 0);

0.4,6.VS,11.VA,16.VB,21.RC,22.774:VXR:av:vcmpgtsbx %VD, %VA, %VB:Vector Compare Greater-Than Signed Byte
	int i;
	signed8 a, b;
	for (i = 0; i < 16; i++) {
	  a = (*vA).b[i];
	  b = (*vB).b[i];
	  if (a > b)
	    (*vS).b[i] = 0xff;