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Set the size of the cache used to hold decoded instructions.

Psim executes instructions in two separate steps:

	o	instruction fetch/decode

	o	instruction execution

For a given instruction, the first stage need only be executed once
(the first time the instruction is encountered) while the second stage
must be executed every time the program `executes' that instruction.

Exploiting this, PSIM can maintain a cache of decoded instructions.
It will then use the decoded instruction from the cache in preference
to fetching/decoding the real instruction from memory.

Ex: default

Because this feature is normally such a big win, it is enabled by
default (with the cache size set to 1024 entries).

The 1024 entries equals 4096 bytes (or one page) of instructions.
Larger caches can be used but with caution - PSIM does not check for
address aliasing within its instruction cache.

Ex: disable the cache

There may be cases (for instance where the cache has a low hit rate)
where the psim performs better with no instruction cache.  For such
situations, the cache can be disabled vis: --disable-sim-icache.



--enable-sim-inline[=module]


Specify the inlining of one or more modules.

Many architectures (in particular the x86) suffer from a large
function call overhead.  By eliminating function calls (through
inlining of functions) a large performance gain can be achieved.

In PSIM, modules are inlined in one of two possible ways.  Some
modules (such as the byte swapping code) can be inlined into any
module that calls them.  Other modules, due to complex
interdependencies, are only inlined as a group when compiling the
external interface module psim.c.

Ex: default

By default the modules endian (handle be/le), bits (manipulate
bit-fields within words), cpu (the processor object) and events
(timers) are inlined in any module that calls them.  This gives a
reasonable performance gain with little additional compilation
overhead.

Ex: recommended  --enable-sim-inline

Assuming you machine is reasonably well configured, this option is
highly recommended.  On the x86 several orders of magnitude
improvement in performance is possible.

Ex: fine tuning

The file std-config.h contains a detailed description of how the
inlining works.  Individual modules can be inlined by specifying them.
For if you have a very large cache the model module could be inlined
with:

	--enable-sim-inline=MODEL



--enable-sim-bswap


(x86 specific) Use the i486/P5/P6 byte swap instruction.

PSIM contains generic byte swapping code.  For the x86 (P[4-6]) PSIM
can be built so that it uses the bswap instruction instead of relying
on the compiler to generate byte swap code.

Ex: default

By default, when compiling with GCC-2 on an i486/P5/P6 the bswap
instruction is used.



--enable-sim-endian=endian


Specify the byte order of the target.

By default, PSIM is able to execute both big and little endian
executables.  As a consequence, every byte swap routine includes a
test to see if the byte swap is really needed.  By specifying the byte
order of the target (and the host below) the need for this test can be
eliminated.

Clearly setting the byte order of the target is only useful when known
before hand.



--enable-sim-hostendain=end


As above but for the host.

Normally this option should not be needed. configure (autoconf) should
determine the byte order of the host automatically.  However if for
some reason there is a problem, this option can be used to override
autoconf.



--enable-sim-smp=n


Set the maximum number of processors that PSIM can model.

Psim can model (with small limitation discussed else where) a
multi-processor PowerPC environment.  While the overhead of
co-ordinating the execution of a number of processors is relatively
small it is still significant when compared to handling only one
processor.

This option only sets the maximum number of processors that can be
simulated.  The number active during a given simulation run us
determined at run time.

Ex: default

By default 5 processors are configured but only one is enabled.
Additional processors can be enabled with the runtime option:

	-o '/openprom/options/smp 5'

Ex: recommended

Unless you intend studying multi-processor systems there is little reason for
having PSIM configured with SMP support.  Specifying:

	--disable-sim-smp
or	--enable-sim-smp=0

will eliminate any SMP such as:

	for (cpu = 0; cpu < nr_cpus; cpu++)
		...



--enable-sim-xor-endian=n


Set the byte-size of the bus involved in the PowerPC's xor endian byte
swapping.

The PowerPC's implementation of BE/LE mode is different to what a
programmer may first expect.  The details of this implementation are
discussed at length in PowerPC documentation.

Ex: default

By default this is configured with a value of 8 (the bus size of most
60x processors).

Ex: recommended

Unless you are expecting to test/debug PowerPC be/le switching code
this option is of little use and should be disabled:

	--disable-sim-xor-endian



--enable-sim-bitsize=n


Specify the bit size (32/64) of the PowerPC to be modelled.

Note: By default 32 is specified.  The implementation of the 64bit
architecture is still under development.


--enable-sim-hostbitsize=32|64

As above but for the host.

NOTE: Psim has yet to be built on a 64bit host.



--enable-sim-env=env


Hardwire the PowerPC environment being modelled (user, virtual or
operating).

The PowerPC architecture defines three different levels of compliance to its
architectural specification.  These environments are discussed in detail in
PowerPC publications.

	user - normal user programs 
	virtual - an extension of the user environment (includes timers)
	operating - kernel code

Ex: default

By default all three environments are supported.

Ex: recommended

If you only intend running psim with user (or operating) code then
PSIM should be configured accordingly.  For user code, it eliminates:
support for timers and events and redundant VM calls.



--enable-sim-timebase


Enable/disable the time base register.

The PowerPC architecture (virtual environment) includes a time base
register.  Maintaining that register incurs an overhead in
performance that can be eliminated by eliminating time-base register
support.

Ex: default

Normally this option is not used.  Instead --enable-sim-env (above) us
used to disable/enable features such as the timebase register.



--enable-sim-alignment=align


Control the PowerPC's memory access alignment restrictions.

The PowerPC in LE mode only allows memory transfers of a correctly
aligned size/address.  The above option controls how misaligned
accesses are handled.

	strict		All accesses must be correctly aligned

	nonstrict	Unaligned access allowed (the are split
			into a number of aligned accesses).

Ex: default

Unless otherwise specified PSIM will auto configure a BE program to
allow miss-aligned accesses while a LE program will not.

Ex: 604e

The recently announced 604e processor allows miss-aligned accesses in both
BE and LE modes.  If modeling the 604e then you should specify:

	--enable-sim-alignment=nonstrict



--enable-sim-trace


Include code to trace PSIM's internal progress (also controlled by the
-t option).

Checking to see if a trace message should be output slows down a
simulation.  Disabling this option (--disable-sim-trace) eliminates
completely that code.



--enable-sim-assert


Include the code that checks the correctness of parts of PSIM.

Eliminating such code (--disable-sim-assert) eliminates internal
consistency tests and their overhead.



--enable-sim-reserved-bits


Include code to check that the reserved fields of the instruction are
zero.

The PowerPC architecture defines certain fields of some instructions
as reserved (`/').  By default, for each instruction, PSIM will check
the reserved fields causing an invalid instruction exception if a
field is invalid.  Disabling this option eliminates this test.  This
is at the slight risk of PSIM treating an invalid instruction as
valid.



--enable-sim-float


Include support for hardware floating point.



--enable-sim-monitor=mon


Include support for basic instruction counting.

If you are not interested in the performance of either you program or
the simulator then you can disable this option.



--enable-sim-model=which

Hardwire the processor that will be used as a reference when modeling
execution units.



--enable-sim-default-model=which


Specify the processor of choice for the execution unit model.



--enable-sim-model-issue


Include support for the modeling of processor execution units.

    ----------------------------------------------------------------------

TYPICAL CONFIGURATION OPTIONS:


	VEA CODE ONLY:

	Here of note are:

		o	ramp up the compiler options (some
			of the below are P5 specific).

		o	disable anything not used

        CC=gcc ./configure \
                --prefix=/applications/psim \
                --target=powerpc-unknown-eabi \
                --enable-sim-powerpc \
                --enable-sim-warnings \
                --enable-sim-inline \
                --disable-sim-smp \
                --enable-sim-duplicate \
                --enable-sim-endian=big \
                --disable-sim-xor-endian \
                --enable-sim-env=user \
                --disable-sim-reserved-bits \
                --disable-sim-assert \
                --disable-sim-trace \
                --enable-sim-cflags='-g0,-O2,-fno-strength-reduce,-fomit-frame-pointer'


	OEA CODE ONLY:

	The key configuration changes are:

		o	turn off the instruction cache.  The overhead
			of flushing and reloading it is greater than
			not having a cache.

		o	use a switch statement (ppc-opcode-flat) for
			the instruction decode and then (-O3) fully
			inline all functions.

		o	--enable-sim-warnings is not present.  GCC (2.7.2)
			gets confused by the instruction decode table
			generated by igen (contains a perfect switch)
			and, as a consequence, generates a bogus warning.

	CC=gcc ./configure \
                --prefix=/applications/psim \
                --target=powerpc-unknown-eabi \
                --enable-sim-powerpc \
                --enable-sim-inline \
                --disable-sim-smp \
                --enable-sim-duplicate \
                --enable-sim-endian=big \
                --disable-sim-xor-endian \
                --enable-sim-env=operating \
                --disable-sim-reserved-bits \
                --disable-sim-assert \
                --disable-sim-trace \
                --enable-sim-opcode=ppc-opcode-flat \
                --disable-sim-icache \
                --enable-sim-cflags='-g0,-O3,-fno-strength-reduce,-fomit-frame-pointer'