📄 sim-trace.h
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sim_cpu *cpu, int trace_idx, int d0));extern void trace_input_fp1 PARAMS ((SIM_DESC sd, sim_cpu *cpu, int trace_idx, fp_word f0));extern void trace_input_fp2 PARAMS ((SIM_DESC sd, sim_cpu *cpu, int trace_idx, fp_word f0, fp_word f1));extern void trace_input_fp3 PARAMS ((SIM_DESC sd, sim_cpu *cpu, int trace_idx, fp_word f0, fp_word f1, fp_word f2));extern void trace_input_fpu1 PARAMS ((SIM_DESC sd, sim_cpu *cpu, int trace_idx, struct _sim_fpu *f0));extern void trace_input_fpu2 PARAMS ((SIM_DESC sd, sim_cpu *cpu, int trace_idx, struct _sim_fpu *f0, struct _sim_fpu *f1));extern void trace_input_fpu3 PARAMS ((SIM_DESC sd, sim_cpu *cpu, int trace_idx, struct _sim_fpu *f0, struct _sim_fpu *f1, struct _sim_fpu *f2));/* Other trace_input{_<fmt><nr-inputs>} functions can go here */extern void trace_result0 PARAMS ((SIM_DESC sd, sim_cpu *cpu, int trace_idx));extern void trace_result_word1 PARAMS ((SIM_DESC sd, sim_cpu *cpu, int trace_idx, unsigned_word r0));extern void trace_result_word2 PARAMS ((SIM_DESC sd, sim_cpu *cpu, int trace_idx, unsigned_word r0, unsigned_word r1));extern void trace_result_word4 PARAMS ((SIM_DESC sd, sim_cpu *cpu, int trace_idx, unsigned_word r0, unsigned_word r1, unsigned_word r2, unsigned_word r3));extern void trace_result_bool1 PARAMS ((SIM_DESC sd, sim_cpu *cpu, int trace_idx, int r0));extern void trace_result_addr1 PARAMS ((SIM_DESC sd, sim_cpu *cpu, int trace_idx, address_word r0));extern void trace_result_fp1 PARAMS ((SIM_DESC sd, sim_cpu *cpu, int trace_idx, fp_word f0));extern void trace_result_fp2 PARAMS ((SIM_DESC sd, sim_cpu *cpu, int trace_idx, fp_word f0, fp_word f1));extern void trace_result_fpu1 PARAMS ((SIM_DESC sd, sim_cpu *cpu, int trace_idx, struct _sim_fpu *f0));extern void trace_result_string1 PARAMS ((SIM_DESC sd, sim_cpu *cpu, int trace_idx, char *str0));extern void trace_result_word1_string1 PARAMS ((SIM_DESC sd, sim_cpu *cpu, int trace_idx, unsigned_word r0, char *s0));/* Other trace_result{_<type><nr-results>} *//* Macros for tracing ALU instructions */#define TRACE_ALU_INPUT0() \do { \ if (TRACE_ALU_P (CPU)) \ trace_input0 (SD, CPU, TRACE_ALU_IDX); \} while (0) #define TRACE_ALU_INPUT1(V0) \do { \ if (TRACE_ALU_P (CPU)) \ trace_input_word1 (SD, CPU, TRACE_ALU_IDX, (V0)); \} while (0)#define TRACE_ALU_INPUT2(V0,V1) \do { \ if (TRACE_ALU_P (CPU)) \ trace_input_word2 (SD, CPU, TRACE_ALU_IDX, (V0), (V1)); \} while (0)#define TRACE_ALU_INPUT3(V0,V1,V2) \do { \ if (TRACE_ALU_P (CPU)) \ trace_input_word3 (SD, CPU, TRACE_ALU_IDX, (V0), (V1), (V2)); \} while (0)#define TRACE_ALU_INPUT4(V0,V1,V2,V3) \do { \ if (TRACE_ALU_P (CPU)) \ trace_input_word4 (SD, CPU, TRACE_ALU_IDX, (V0), (V1), (V2), (V3)); \} while (0)#define TRACE_ALU_RESULT(R0) TRACE_ALU_RESULT1(R0)#define TRACE_ALU_RESULT0() \do { \ if (TRACE_ALU_P (CPU)) \ trace_result0 (SD, CPU, TRACE_ALU_IDX); \} while (0)#define TRACE_ALU_RESULT1(R0) \do { \ if (TRACE_ALU_P (CPU)) \ trace_result_word1 (SD, CPU, TRACE_ALU_IDX, (R0)); \} while (0)#define TRACE_ALU_RESULT2(R0,R1) \do { \ if (TRACE_ALU_P (CPU)) \ trace_result_word2 (SD, CPU, TRACE_ALU_IDX, (R0), (R1)); \} while (0)#define TRACE_ALU_RESULT4(R0,R1,R2,R3) \do { \ if (TRACE_ALU_P (CPU)) \ trace_result_word4 (SD, CPU, TRACE_ALU_IDX, (R0), (R1), (R2), (R3)); \} while (0)/* Macros for tracing inputs to comparative branch instructions. */#define TRACE_BRANCH_INPUT1(V0) \do { \ if (TRACE_BRANCH_P (CPU)) \ trace_input_word1 (SD, CPU, TRACE_BRANCH_IDX, (V0)); \} while (0)#define TRACE_BRANCH_INPUT2(V0,V1) \do { \ if (TRACE_BRANCH_P (CPU)) \ trace_input_word2 (SD, CPU, TRACE_BRANCH_IDX, (V0), (V1)); \} while (0)/* Macros for tracing FPU instructions */#define TRACE_FP_INPUT0() \do { \ if (TRACE_FPU_P (CPU)) \ trace_input0 (SD, CPU, TRACE_FPU_IDX); \} while (0) #define TRACE_FP_INPUT1(V0) \do { \ if (TRACE_FPU_P (CPU)) \ trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, (V0)); \} while (0)#define TRACE_FP_INPUT2(V0,V1) \do { \ if (TRACE_FPU_P (CPU)) \ trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \} while (0)#define TRACE_FP_INPUT3(V0,V1,V2) \do { \ if (TRACE_FPU_P (CPU)) \ trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, (V0), (V1), (V2)); \} while (0)#define TRACE_FP_INPUT_WORD1(V0) \do { \ if (TRACE_FPU_P (CPU)) \ trace_input_word1 (SD, CPU, TRACE_FPU_IDX, (V0)); \} while (0) #define TRACE_FP_RESULT(R0) \do { \ if (TRACE_FPU_P (CPU)) \ trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, (R0)); \} while (0)#define TRACE_FP_RESULT2(R0,R1) \do { \ if (TRACE_FPU_P (CPU)) \ trace_result_fp2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \} while (0)#define TRACE_FP_RESULT_BOOL(R0) \do { \ if (TRACE_FPU_P (CPU)) \ trace_result_bool1 (SD, CPU, TRACE_FPU_IDX, (R0)); \} while (0)#define TRACE_FP_RESULT_WORD(R0) \do { \ if (TRACE_FPU_P (CPU)) \ trace_result_word1 (SD, CPU, TRACE_FPU_IDX, (R0)); \} while (0)/* Macros for tracing branches */#define TRACE_BRANCH_INPUT(COND) \do { \ if (TRACE_BRANCH_P (CPU)) \ trace_input_bool1 (SD, CPU, TRACE_BRANCH_IDX, (COND)); \} while (0)#define TRACE_BRANCH_RESULT(DEST) \do { \ if (TRACE_BRANCH_P (CPU)) \ trace_result_addr1 (SD, CPU, TRACE_BRANCH_IDX, (DEST)); \} while (0)/* The function trace_one_insn has been replaced by the function pair trace_prefix() + trace_generic() */extern void trace_one_insn PARAMS ((SIM_DESC sd, sim_cpu * cpu, address_word cia, int print_linenum_p, const char *file_name, int line_nr, const char *unit, const char *fmt, ...)) __attribute__((format (printf, 8, 9)));extern void trace_printf PARAMS ((SIM_DESC, sim_cpu *, const char *, ...)) __attribute__((format (printf, 3, 4)));extern void trace_vprintf PARAMS ((SIM_DESC, sim_cpu *, const char *, va_list));/* Debug support. This is included here because there isn't enough of it to justify a sim-debug.h. *//* Return non-zero if debugging of IDX for CPU is enabled. */#define DEBUG_P(cpu, idx) \((WITH_DEBUG & (1 << (idx))) != 0 \ && CPU_DEBUG_FLAGS (cpu)[idx] != 0)/* Non-zero if "--debug-insn" specified. */#define DEBUG_INSN_P(cpu) DEBUG_P (cpu, DEBUG_INSN_IDX)extern void debug_printf PARAMS ((sim_cpu *, const char *, ...)) __attribute__((format (printf, 2, 3)));#endif /* SIM_TRACE_H */
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