sim-core.c

gdb-6.0 linux 下的调试工具

	  && (*entry)->space == space)
	{
	  sim_core_mapping *dead = (*entry);
	  (*entry) = dead->next;
	  if (dead->free_buffer != NULL)
	    zfree (dead->free_buffer);
	  zfree (dead);
	  return;
	}
    }
}
#endif

#if EXTERN_SIM_CORE_P
void
sim_core_detach (SIM_DESC sd,
		 sim_cpu *cpu,
		 int level,
		 int address_space,
		 address_word addr)
{
  sim_core *memory = STATE_CORE (sd);
  unsigned map;
  for (map = 0; map < nr_maps; map++)
    {
      sim_core_map_detach (sd, &memory->common.map[map],
			   level, address_space, addr);
    }
  /* Just copy this update to each of the processor specific data
     structures.  FIXME - later this will be replaced by true
     processor specific maps. */
  {
    int i;
    for (i = 0; i < MAX_NR_PROCESSORS; i++)
      {
	CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
      }
  }
}
#endif


STATIC_INLINE_SIM_CORE\
(sim_core_mapping *)
sim_core_find_mapping(sim_core_common *core,
		      unsigned map,
		      address_word addr,
		      unsigned nr_bytes,
		      transfer_type transfer,
		      int abort, /*either 0 or 1 - hint to inline/-O */
		      sim_cpu *cpu, /* abort => cpu != NULL */
		      sim_cia cia)
{
  sim_core_mapping *mapping = core->map[map].first;
  ASSERT ((addr & (nr_bytes - 1)) == 0); /* must be aligned */
  ASSERT ((addr + (nr_bytes - 1)) >= addr); /* must not wrap */
  ASSERT (!abort || cpu != NULL); /* abort needs a non null CPU */
  while (mapping != NULL)
    {
      if (addr >= mapping->base
	  && (addr + (nr_bytes - 1)) <= mapping->bound)
	return mapping;
      mapping = mapping->next;
    }
  if (abort)
    {
      SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, nr_bytes, addr, transfer,
		       sim_core_unmapped_signal);
    }
  return NULL;
}


STATIC_INLINE_SIM_CORE\
(void *)
sim_core_translate (sim_core_mapping *mapping,
		    address_word addr)
{
  if (WITH_MODULO_MEMORY)
    return (void *)((unsigned8 *) mapping->buffer
		    + ((addr - mapping->base) & mapping->mask));
  else
    return (void *)((unsigned8 *) mapping->buffer
		    + addr - mapping->base);
}


#if EXTERN_SIM_CORE_P
unsigned
sim_core_read_buffer (SIM_DESC sd,
		      sim_cpu *cpu,
		      unsigned map,
		      void *buffer,
		      address_word addr,
		      unsigned len)
{
  sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
  unsigned count = 0;
  while (count < len)
 {
    unsigned_word raddr = addr + count;
    sim_core_mapping *mapping =
      sim_core_find_mapping (core, map,
			    raddr, /*nr-bytes*/1,
			    read_transfer,
			    0 /*dont-abort*/, NULL, NULL_CIA);
    if (mapping == NULL)
      break;
#if (WITH_DEVICES)
    if (mapping->device != NULL)
      {
	int nr_bytes = len - count;
	sim_cia cia = cpu ? CIA_GET (cpu) : NULL_CIA;
	if (raddr + nr_bytes - 1> mapping->bound)
	  nr_bytes = mapping->bound - raddr + 1;
	if (device_io_read_buffer (mapping->device,
				   (unsigned_1*)buffer + count,
				   mapping->space,
				   raddr,
				   nr_bytes, 
				   sd,
				   cpu, 
				   cia) != nr_bytes)
	  break;
	count += nr_bytes;
	continue;
      }
#endif
#if (WITH_HW)
    if (mapping->device != NULL)
      {
	int nr_bytes = len - count;
	if (raddr + nr_bytes - 1> mapping->bound)
	  nr_bytes = mapping->bound - raddr + 1;
	if (sim_hw_io_read_buffer (sd, mapping->device,
				   (unsigned_1*)buffer + count,
				   mapping->space,
				   raddr,
				   nr_bytes) != nr_bytes)
	  break;
	count += nr_bytes;
	continue;
      }
#endif
    ((unsigned_1*)buffer)[count] =
      *(unsigned_1*)sim_core_translate(mapping, raddr);
    count += 1;
 }
  return count;
}
#endif


#if EXTERN_SIM_CORE_P
unsigned
sim_core_write_buffer (SIM_DESC sd,
		       sim_cpu *cpu,
		       unsigned map,
		       const void *buffer,
		       address_word addr,
		       unsigned len)
{
  sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
  unsigned count = 0;
  while (count < len)
    {
      unsigned_word raddr = addr + count;
      sim_core_mapping *mapping =
	sim_core_find_mapping (core, map,
			       raddr, /*nr-bytes*/1,
			       write_transfer,
			       0 /*dont-abort*/, NULL, NULL_CIA);
      if (mapping == NULL)
	break;
#if (WITH_DEVICES)
      if (WITH_CALLBACK_MEMORY
	  && mapping->device != NULL)
	{
	  int nr_bytes = len - count;
	  sim_cia cia = cpu ? CIA_GET (cpu) : NULL_CIA;
	  if (raddr + nr_bytes - 1 > mapping->bound)
	    nr_bytes = mapping->bound - raddr + 1;
	  if (device_io_write_buffer (mapping->device,
				      (unsigned_1*)buffer + count,
				      mapping->space,
				      raddr,
				      nr_bytes,
				      sd,
				      cpu, 
				      cia) != nr_bytes)
	    break;
	  count += nr_bytes;
	  continue;
	}
#endif
#if (WITH_HW)
      if (WITH_CALLBACK_MEMORY
	  && mapping->device != NULL)
	{
	  int nr_bytes = len - count;
	  if (raddr + nr_bytes - 1 > mapping->bound)
	    nr_bytes = mapping->bound - raddr + 1;
	  if (sim_hw_io_write_buffer (sd, mapping->device,
				      (unsigned_1*)buffer + count,
				      mapping->space,
				      raddr,
				      nr_bytes) != nr_bytes)
	    break;
	  count += nr_bytes;
	  continue;
	}
#endif
      *(unsigned_1*)sim_core_translate(mapping, raddr) =
	((unsigned_1*)buffer)[count];
      count += 1;
    }
  return count;
}
#endif


#if EXTERN_SIM_CORE_P
void
sim_core_set_xor (SIM_DESC sd,
		  sim_cpu *cpu,
		  int is_xor)
{
  /* set up the XOR map if required. */
  if (WITH_XOR_ENDIAN) {
    {
      sim_core *core = STATE_CORE (sd);
      sim_cpu_core *cpu_core = (cpu != NULL ? CPU_CORE (cpu) : NULL);
      if (cpu_core != NULL)
	{
	  int i = 1;
	  unsigned mask;
	  if (is_xor)
	    mask = WITH_XOR_ENDIAN - 1;
	  else
	    mask = 0;
	  while (i - 1 < WITH_XOR_ENDIAN)
	    {
	      cpu_core->xor[i-1] = mask;
	      mask = (mask << 1) & (WITH_XOR_ENDIAN - 1);
	      i = (i << 1);
	    }
	}
      else
	{
	  if (is_xor)
	    core->byte_xor = WITH_XOR_ENDIAN - 1;
	  else
	    core->byte_xor = 0;
	}	  
    }
  }
  else {
    if (is_xor)
      sim_engine_abort (sd, NULL, NULL_CIA,
			"Attempted to enable xor-endian mode when permenantly disabled.");
  }
}
#endif


#if EXTERN_SIM_CORE_P
static void
reverse_n (unsigned_1 *dest,
	   const unsigned_1 *src,
	   int nr_bytes)
{
  int i;
  for (i = 0; i < nr_bytes; i++)
    {
      dest [nr_bytes - i - 1] = src [i];
    }
}
#endif


#if EXTERN_SIM_CORE_P
unsigned
sim_core_xor_read_buffer (SIM_DESC sd,
			  sim_cpu *cpu,
			  unsigned map,
			  void *buffer,
			  address_word addr,
			  unsigned nr_bytes)
{
  address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
  if (!WITH_XOR_ENDIAN || !byte_xor)
    return sim_core_read_buffer (sd, cpu, map, buffer, addr, nr_bytes);
  else
    /* only break up transfers when xor-endian is both selected and enabled */
    {
      unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */
      unsigned nr_transfered = 0;
      address_word start = addr;
      unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
      address_word stop;
      /* initial and intermediate transfers are broken when they cross
         an XOR endian boundary */
      while (nr_transfered + nr_this_transfer < nr_bytes)
	/* initial/intermediate transfers */
	{
	  /* since xor-endian is enabled stop^xor defines the start
             address of the transfer */
	  stop = start + nr_this_transfer - 1;
	  SIM_ASSERT (start <= stop);
	  SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
	  if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
	      != nr_this_transfer)
	    return nr_transfered;
	  reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
	  nr_transfered += nr_this_transfer;
	  nr_this_transfer = WITH_XOR_ENDIAN;
	  start = stop + 1;
	}
      /* final transfer */
      nr_this_transfer = nr_bytes - nr_transfered;
      stop = start + nr_this_transfer - 1;
      SIM_ASSERT (stop == (addr + nr_bytes - 1));
      if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
	  != nr_this_transfer)
	return nr_transfered;
      reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
      return nr_bytes;
    }
}
#endif
  
  
#if EXTERN_SIM_CORE_P
unsigned
sim_core_xor_write_buffer (SIM_DESC sd,
			   sim_cpu *cpu,
			   unsigned map,
			   const void *buffer,
			   address_word addr,
			   unsigned nr_bytes)
{
  address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
  if (!WITH_XOR_ENDIAN || !byte_xor)
    return sim_core_write_buffer (sd, cpu, map, buffer, addr, nr_bytes);
  else
    /* only break up transfers when xor-endian is both selected and enabled */
    {
      unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero sized array */
      unsigned nr_transfered = 0;
      address_word start = addr;
      unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
      address_word stop;
      /* initial and intermediate transfers are broken when they cross
         an XOR endian boundary */
      while (nr_transfered + nr_this_transfer < nr_bytes)
	/* initial/intermediate transfers */
	{
	  /* since xor-endian is enabled stop^xor defines the start
             address of the transfer */
	  stop = start + nr_this_transfer - 1;
	  SIM_ASSERT (start <= stop);
	  SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
	  reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
	  if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
	      != nr_this_transfer)
	    return nr_transfered;
	  nr_transfered += nr_this_transfer;
	  nr_this_transfer = WITH_XOR_ENDIAN;
	  start = stop + 1;
	}
      /* final transfer */
      nr_this_transfer = nr_bytes - nr_transfered;
      stop = start + nr_this_transfer - 1;
      SIM_ASSERT (stop == (addr + nr_bytes - 1));
      reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
      if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
	  != nr_this_transfer)
	return nr_transfered;
      return nr_bytes;
    }
}
#endif



/* define the read/write 1/2/4/8/16/word functions */

#define N 16
#include "sim-n-core.h"

#define N 8
#include "sim-n-core.h"

#define N 7
#define M 8
#include "sim-n-core.h"

#define N 6
#define M 8
#include "sim-n-core.h"

#define N 5
#define M 8
#include "sim-n-core.h"

#define N 4
#include "sim-n-core.h"

#define N 3
#define M 4
#include "sim-n-core.h"

#define N 2
#include "sim-n-core.h"

#define N 1
#include "sim-n-core.h"

#endif