movb.s

gdb-6.0 linux 下的调试工具

	test_gr_a5a5 2		; to examine the destination memory).
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	mov.b	@byte_dst, r0l
	cmp.b	r0l, r1l
	beq	.Lnext41
	fail
.Lnext41:
	mov.b	#0, r0l
	mov.b	r0l, @byte_dst	; zero it again for the next use.

mov_b_reg8_to_abs32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.b ers, @aa:32
	mov.b	r0l, @byte_dst:32	; 32-bit address-direct operand
;;;	.word	0x6aa8
;;;	.long	@byte_dst

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
	test_gr_a5a5 1		; (first, because on h8/300 we must use one
	test_gr_a5a5 2		; to examine the destination memory).
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	mov.b	@byte_dst, r0l
	cmp.b	r0l, r1l
	beq	.Lnext42
	fail
.Lnext42:
	mov.b	#0, r0l
	mov.b	r0l, @byte_dst	; zero it again for the next use.

	;;
	;; Move byte to register destination.
	;; 

mov_b_indirect_to_reg8:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.b @ers, rd
	mov.l	#byte_src, er1
	mov.b	@er1, r0l	; Register indirect operand
;;;	.word	0x6818

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a5a577 er0

	test_h_gr32	byte_src, er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

mov_b_postinc_to_reg8:		; post-increment from mem to register
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.b @ers+, rd

	mov.l	#byte_src, er1
	mov.b	@er1+, r0l	; Register post-incr operand
;;;	.word	0x6c18

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a5a577 er0

	test_h_gr32	byte_src+1, er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

.if (sim_cpu == h8sx)
mov_b_postdec_to_reg8:		; post-decrement from mem to register
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.b @ers-, rd

	mov.l	#byte_src, er1
	mov.b	@er1-, r0l	; Register post-decr operand
;;;	.word	0x0172
;;;	.word	0x6c18

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a5a577 er0

	test_h_gr32	byte_src-1, er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

mov_b_preinc_to_reg8:		; pre-increment from mem to register
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.b @+ers, rd

	mov.l	#byte_src-1, er1
	mov.b	@+er1, r0l	; Register pre-incr operand
;;;	.word	0x0171
;;;	.word	0x6c18

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a5a577 er0

	test_h_gr32	byte_src, er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

mov_b_predec_to_reg8:		; pre-decrement from mem to register
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.b @-ers, rd

	mov.l	#byte_src+1, er1
	mov.b	@-er1, r0l	; Register pre-decr operand
;;;	.word	0x0173
;;;	.word	0x6c18

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a5a577 er0

	test_h_gr32	byte_src, er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	
mov_b_disp2_to_reg8:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.b @(dd:2, ers), rd
	mov.l	#byte_src-1, er1
	mov.b	@(1:2, er1), r0l	; Register plus 2-bit disp. operand
;;; 	.word	0x0171
;;; 	.word	0x6818

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a5a577 er0	; mov result:	a5a5 | 7777

	test_h_gr32	byte_src-1, er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7
.endif

mov_b_disp16_to_reg8:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.b @(dd:16, ers), rd
	mov.l	#byte_src+0x1234, er1
	mov.b	@(-0x1234:16, er1), r0l	; Register plus 16-bit disp. operand
;;;	.word	0x6e18
;;;	.word	-0x1234

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a5a577 er0	; mov result:	a5a5 | 7777

	test_h_gr32	byte_src+0x1234, er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

mov_b_disp32_to_reg8:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.b @(dd:32, ers), rd
	mov.l	#byte_src+65536, er1
	mov.b	@(-65536:32, er1), r0l	; Register plus 32-bit disp. operand
;;;	.word	0x7810
;;;	.word	0x6a28
;;;	.long	-65536

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a5a577 er0	; mov result:	a5a5 | 7777

	test_h_gr32	byte_src+65536, er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

.if (sim_cpu == h8sx)
mov_b_indexb16_to_reg8:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	mov.l	#0xffffff01, er1
	set_ccr_zero
	;; mov.b @(dd:16, rs.b), rd
	mov.b	@(byte_src-1:16, r1.b), r0l	; indexed byte operand

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a5a577 er0	; mov result:	a5a5a5 | 77

	test_h_gr32  0xffffff01, er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

mov_b_indexw16_to_reg8:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	mov.l	#0xffff0002, er1
	set_ccr_zero
	;; mov.b @(dd:16, rs.w), rd
	mov.b	@(byte_src-2:16, r1.w), r0l	; indexed byte operand

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a5a577 er0	; mov result:	a5a5a5 | 77

	test_h_gr32  0xffff0002, er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

mov_b_indexl16_to_reg8:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	mov.l	#0x00000003, er1
	set_ccr_zero
	;; mov.b @(dd:16, ers.l), rd
	mov.b	@(byte_src-3:16, er1.l), r0l	; indexed byte operand

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a5a577 er0	; mov result:	a5a5a5 | 77

	test_h_gr32  0x00000003, er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

mov_b_indexb32_to_reg8:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	mov.l	#0xffffff04, er1
	set_ccr_zero
	;; mov.b @(dd:32, rs.b), rd
	mov.b	@(byte_src-4:32, r1.b), r0l	; indexed byte operand

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a5a577 er0	; mov result:	a5a5 | 7777

	test_h_gr32  0xffffff04 er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

mov_b_indexw32_to_reg8:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	mov.l	#0xffff0005, er1
	set_ccr_zero
	;; mov.b @(dd:32, rs.w), rd
	mov.b	@(byte_src-5:32, r1.w), r0l	; indexed byte operand

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a5a577 er0	; mov result:	a5a5 | 7777

	test_h_gr32  0xffff0005 er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

mov_b_indexl32_to_reg8:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	mov.l	#0x00000006, er1
	set_ccr_zero
	;; mov.b @(dd:32, ers.l), rd
	mov.b	@(byte_src-6:32, er1.l), r0l	; indexed byte operand

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a5a577 er0	; mov result:	a5a5 | 7777

	test_h_gr32  0x00000006 er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

.endif

.if (sim_cpu == h8sx)
mov_b_abs8_to_reg8:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	mov.l	#byte_src-255, er1
	ldc	er1, sbr
	set_ccr_zero
	;; mov.b @aa:8, rd
	mov.b	@0xff:8, r0l	; 8-bit (sbr relative) address-direct operand

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a5a577 er0

	test_h_gr32  byte_src-255, er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7
.endif

mov_b_abs16_to_reg8:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.b @aa:16, rd
	mov.b	@byte_src:16, r0l	; 16-bit address-direct operand
;;;	.word	0x6a08
;;;	.word	@byte_src

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a5a577 er0

	test_gr_a5a5 1		; Make sure other general regs not disturbed
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

mov_b_abs32_to_reg8:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.b @aa:32, rd
	mov.b	@byte_src:32, r0l	; 32-bit address-direct operand
;;;	.word	0x6a28
;;;	.long	@byte_src

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a5a577 er0

	test_gr_a5a5 1		; Make sure other general regs not disturbed
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

.if (sim_cpu == h8sx)

	;;
	;; Move byte from memory to memory
	;; 

mov_b_indirect_to_indirect:	; reg indirect, memory to memory
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.b @ers, @erd

	mov.l	#byte_src, er1
	mov.l	#byte_dst, er0
	mov.b	@er1, @er0
;;;	.word	0x0178
;;;	.word	0x0100

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	;; Verify the affected registers.

	test_h_gr32  byte_dst er0
	test_h_gr32  byte_src er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.b	@byte_src, @byte_dst
	beq	.Lnext55
	fail
.Lnext55:
	;; Now clear the destination location, and verify that.
	mov.b	#0, @byte_dst
	cmp.b	@byte_src, @byte_dst
	bne	.Lnext56
	fail
.Lnext56:			; OK, pass on.

mov_b_postinc_to_postinc:	; reg post-increment, memory to memory
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.b @ers+, @erd+

	mov.l	#byte_src, er1
	mov.l	#byte_dst, er0
	mov.b	@er1+, @er0+
;;;	.word	0x0178
;;;	.word	0x8180

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	;; Verify the affected registers.

	test_h_gr32  byte_dst+1 er0
	test_h_gr32  byte_src+1 er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4