movw.s

gdb-6.0 linux 下的调试工具

	;; Now check the result of the move to memory.
	cmp.w	#0xdead, @word_dst
	beq	.Lnext15
	fail
.Lnext15:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_imm16_to_disp2:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:16, @(dd:2, erd)
	mov.l	#word_dst-6, er1
	mov.w	#0xdead:16, @(6:2, er1)	; Imm16, reg plus 2-bit disp. operand
;;;	.word	0x7974
;;;	.word	0xdead
;;;	.word	0x3100

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst-6, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	#0xdead, @word_dst
	beq	.Lnext16
	fail
.Lnext16:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_imm16_to_disp16:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:16, @(dd:16, erd)
	mov.l	#word_dst-4, er1
	mov.w	#0xdead:16, @(4:16, er1)	; Register plus 16-bit disp. operand
;;;	.word	0x7974
;;;	.word	0xdead
;;;	.word	0xc100
;;;	.word	0x0004

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst-4, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	#0xdead, @word_dst
	beq	.Lnext17
	fail
.Lnext17:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_imm16_to_disp32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:16, @(dd:32, erd)
	mov.l	#word_dst-8, er1
	mov.w	#0xdead:16, @(8:32, er1)   ; Register plus 32-bit disp. operand
;;;	.word	0x7974
;;;	.word	0xdead
;;;	.word	0xc900
;;;	.long	8

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst-8, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	#0xdead, @word_dst
	beq	.Lnext18
	fail
.Lnext18:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_imm16_to_abs16:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:16, @aa:16
	mov.w	#0xdead:16, @word_dst:16	; 16-bit address-direct operand
;;;	.word	0x7974
;;;	.word	0xdead
;;;	.word	0x4000
;;;	.word	@word_dst

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
	test_gr_a5a5 1		; (first, because on h8/300 we must use one
	test_gr_a5a5 2		; to examine the destination memory).
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	#0xdead, @word_dst
	beq	.Lnext19
	fail
.Lnext19:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_imm16_to_abs32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:16, @aa:32
	mov.w	#0xdead:16, @word_dst:32	; 32-bit address-direct operand
;;;	.word	0x7974
;;;	.word	0xdead
;;;	.word	0x4800
;;;	.long	@word_dst

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
	test_gr_a5a5 1		; (first, because on h8/300 we must use one
	test_gr_a5a5 2		; to examine the destination memory).
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	#0xdead, @word_dst
	beq	.Lnext20
	fail
.Lnext20:
	mov.w	#0, @word_dst	; zero it again for the next use.
.endif

	;;
	;; Move word from register source
	;; 

mov_w_reg16_to_reg16:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w ers, erd
	mov.w	#0x1234, r1
	mov.w	r1, r0		; Register 16-bit operand
;;;	.word	0x0d10

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear
	test_h_gr16 0x1234 r0
	test_h_gr16 0x1234 r1	; mov src unchanged
.if (sim_cpu)
	test_h_gr32 0xa5a51234 er0
	test_h_gr32 0xa5a51234 er1	; mov src unchanged
.endif
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7


mov_w_reg16_to_indirect:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w ers, @erd
	mov.l	#word_dst, er1
	mov.w	r0, @er1	; Register indirect operand
;;;	.word	0x6990

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	mov.w	#0, r0
	mov.w	@word_dst, r0
	cmp.w	r2, r0
	beq	.Lnext44
	fail
.Lnext44:
	mov.w	#0, r0
	mov.w	r0, @word_dst	; zero it again for the next use.

.if (sim_cpu == h8sx)
mov_w_reg16_to_postinc:		; post-increment from register to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w ers, @erd+
	mov.l	#word_dst, er1
	mov.w	r0, @er1+	; Register post-incr operand
;;;	.word	0x0153
;;;	.word	0x6d90

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst+2, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	r2, @word_dst
	beq	.Lnext49
	fail
.Lnext49:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_reg16_to_postdec:		; post-decrement from register to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w ers, @erd-
	mov.l	#word_dst, er1
	mov.w	r0, @er1-	; Register post-decr operand
;;;	.word	0x0151
;;;	.word	0x6d90

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst-2, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	r2, @word_dst
	beq	.Lnext50
	fail
.Lnext50:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_reg16_to_preinc:		; pre-increment from register to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w ers, @+erd
	mov.l	#word_dst-2, er1
	mov.w	r0, @+er1	; Register pre-incr operand
;;;	.word	0x0152
;;;	.word	0x6d90

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	r2, @word_dst
	beq	.Lnext51
	fail
.Lnext51:
	mov.w	#0, @word_dst	; zero it again for the next use.
.endif

mov_w_reg16_to_predec:		; pre-decrement from register to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w ers, @-erd
	mov.l	#word_dst+2, er1
	mov.w	r0, @-er1	; Register pre-decr operand
;;;	.word	0x6d90

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	mov.w	#0, r0
	mov.w	@word_dst, r0
	cmp.w	r2, r0
	beq	.Lnext48
	fail
.Lnext48:
	mov.w	#0, r0
	mov.w	r0, @word_dst	; zero it again for the next use.

.if (sim_cpu == h8sx)
mov_w_reg16_to_disp2:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w ers, @(dd:2, erd)
	mov.l	#word_dst-6, er1
	mov.w	r0, @(6:2, er1)	; Register plus 2-bit disp. operand
;;;	.word	0x0153
;;;	.word	0x6990

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst-6, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	r2, @word_dst
	beq	.Lnext52
	fail
.Lnext52:
	mov.w	#0, @word_dst	; zero it again for the next use.
.endif

mov_w_reg16_to_disp16:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w ers, @(dd:16, erd)
	mov.l	#word_dst-4, er1
	mov.w	r0, @(4:16, er1)	; Register plus 16-bit disp. operand
;;;	.word	0x6f90
;;;	.word	0x0004

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32	word_dst-4, er1
	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	mov.w	#0, r0
	mov.w	@word_dst, r0
	cmp.w	r2, r0
	beq	.Lnext45
	fail
.Lnext45:
	mov.w	#0, r0
	mov.w	r0, @word_dst	; zero it again for the next use.

mov_w_reg16_to_disp32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w ers, @(dd:32, erd)
	mov.l	#word_dst-8, er1
	mov.w	r0, @(8:32, er1)	; Register plus 32-bit disp. operand
;;;	.word	0x7810
;;;	.word	0x6ba0
;;;	.long	8

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32	word_dst-8, er1
	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	mov.w	#0, r0
	mov.w	@word_dst, r0
	cmp.w	r2, r0
	beq	.Lnext46
	fail
.Lnext46:
	mov.w	#0, r0
	mov.w	r0, @word_dst	; zero it again for the next use.

mov_w_reg16_to_abs16:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w ers, @aa:16
	mov.w	r0, @word_dst:16	; 16-bit address-direct operand
;;;	.word	0x6b80
;;;	.word	@word_dst

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
	test_gr_a5a5 1		; (first, because on h8/300 we must use one
	test_gr_a5a5 2		; to examine the destination memory).
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	mov.w	#0, r0
	mov.w	@word_dst, r0
	cmp.w	r0, r1
	beq	.Lnext41
	fail
.Lnext41:
	mov.w	#0, r0
	mov.w	r0, @word_dst	; zero it again for the next use.

mov_w_reg16_to_abs32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w ers, @aa:32
	mov.w	r0, @word_dst:32	; 32-bit address-direct operand
;;;	.word	0x6ba0
;;;	.long	@word_dst

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
	test_gr_a5a5 1		; (first, because on h8/300 we must use one
	test_gr_a5a5 2		; to examine the destination memory).
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	mov.w	#0, r0
	mov.w	@word_dst, r0
	cmp.w	r0, r1
	beq	.Lnext42
	fail
.Lnext42:
	mov.w	#0, r0
	mov.w	r0, @word_dst	; zero it again for the next use.

	;;
	;; Move word to register destination.
	;; 

mov_w_indirect_to_reg16:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w @ers, rd
	mov.l	#word_src, er1
	mov.w	@er1, r0	; Register indirect operand
;;;	.word	0x6910

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a57777 er0

	test_h_gr32	word_src, er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

mov_w_postinc_to_reg16:		; post-increment from mem to register
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w @ers+, rd

	mov.l	#word_src, er1
	mov.w	@er1+, r0	; Register post-incr operand
;;;	.word	0x6d10

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a57777 er0

	test_h_gr32	word_src+2, er1
	test_gr_a5a5 2		; Make sure other general regs not disturbed
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

.if (sim_cpu == h8sx)
mov_w_postdec_to_reg16:		; post-decrement from mem to register
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w @ers-, rd

	mov.l	#word_src, er1
	mov.w	@er1-, r0	; Register post-decr operand
;;;	.word	0x0152
;;;	.word	0x6d10

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a57777 er0