movw.s

gdb-6.0 linux 下的调试工具

# Hitachi H8 testcase 'mov.w'
# mach(): h8300h h8300s h8sx
# as(h8300h):	--defsym sim_cpu=1
# as(h8300s):	--defsym sim_cpu=2
# as(h8sx):	--defsym sim_cpu=3
# ld(h8300h):	-m h8300helf
# ld(h8300s):	-m h8300self
# ld(h8sx):	-m h8300sxelf	

	.include "testutils.inc"

	start

	.data
	.align	2
word_src:
	.word	0x7777
word_dst:
	.word	0

	.text

	;;
	;; Move word from immediate source
	;; 

.if (sim_cpu == h8sx)
mov_w_imm3_to_reg16:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:3, rd
	mov.w	#0x3:3, r0	; Immediate 3-bit operand
;;;	.word	0x0f30

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a50003 er0

	test_gr_a5a5 1		; Make sure other general regs not disturbed
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7
.endif

mov_w_imm16_to_reg16:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:16, rd
	mov.w	#0x1234, r0	; Immediate 16-bit operand
;;;	.word	0x7900
;;;	.word	0x1234

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_h_gr32 0xa5a51234 er0

	test_gr_a5a5 1		; Make sure other general regs not disturbed
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

.if (sim_cpu == h8sx)
mov_w_imm4_to_abs16:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:4, @aa:16
	mov.w	#0xf:4, @word_dst:16	; 4-bit imm to 16-bit address-direct 
;;;	.word	0x6bdf
;;;	.word	@word_dst

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
	test_gr_a5a5 1		; (first, because on h8/300 we must use one
	test_gr_a5a5 2		; to examine the destination memory).
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	#0xf, @word_dst
	beq	.Lnext21
	fail
.Lnext21:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_imm4_to_abs32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:4, @aa:32
	mov.w	#0xf:4, @word_dst:32	; 4-bit imm to 32-bit address-direct 
;;;	.word	0x6bff
;;;	.long	@word_dst

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
	test_gr_a5a5 1		; (first, because on h8/300 we must use one
	test_gr_a5a5 2		; to examine the destination memory).
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	#0xf, @word_dst
	beq	.Lnext22
	fail
.Lnext22:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_imm8_to_indirect:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:8, @erd
	mov.l	#word_dst, er1
	mov.w	#0xa5:8, @er1	; Register indirect operand
;;;	.word	0x015d
;;;	.word	0x01a5

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	#0xa5, @word_dst
	beq	.Lnext1
	fail
.Lnext1:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_imm8_to_postinc:		; post-increment from imm8 to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:8, @erd+
	mov.l	#word_dst, er1
	mov.w	#0xa5:8, @er1+	; Imm8, register post-incr operands.
;;;	.word	0x015d
;;;	.word	0x81a5

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst+2, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	#0xa5, @word_dst
	beq	.Lnext2
	fail
.Lnext2:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_imm8_to_postdec:		; post-decrement from imm8 to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:8, @erd-
	mov.l	#word_dst, er1
	mov.w	#0xa5:8, @er1-	; Imm8, register post-decr operands.
;;;	.word	0x015d
;;;	.word	0xa1a5

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst-2, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	#0xa5, @word_dst
	beq	.Lnext3
	fail
.Lnext3:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_imm8_to_preinc:		; pre-increment from register to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:8, @+erd
	mov.l	#word_dst-2, er1
	mov.w	#0xa5:8, @+er1	; Imm8, register pre-incr operands
;;;	.word	0x015d
;;;	.word	0x91a5

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	#0xa5, @word_dst
	beq	.Lnext4
	fail
.Lnext4:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_imm8_to_predec:		; pre-decrement from register to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:8, @-erd
	mov.l	#word_dst+2, er1
	mov.w	#0xa5:8, @-er1	; Imm8, register pre-decr operands
;;;	.word	0x015d
;;;	.word	0xb1a5

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	#0xa5, @word_dst
	beq	.Lnext5
	fail
.Lnext5:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_imm8_to_disp2:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:8, @(dd:2, erd)
	mov.l	#word_dst-6, er1
	mov.w	#0xa5:8, @(6:2, er1)	; Imm8, reg plus 2-bit disp. operand
;;;	.word	0x015d
;;;	.word	0x31a5

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst-6, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	#0xa5, @word_dst
	beq	.Lnext6
	fail
.Lnext6:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_imm8_to_disp16:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:8, @(dd:16, erd)
	mov.l	#word_dst-4, er1
	mov.w	#0xa5:8, @(4:16, er1)	; Register plus 16-bit disp. operand
;;;	.word	0x015d
;;;	.word	0x6f90
;;;	.word	0x0004

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst-4, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	#0xa5, @word_dst
	beq	.Lnext7
	fail
.Lnext7:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_imm8_to_disp32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:8, @(dd:32, erd)
	mov.l	#word_dst-8, er1
	mov.w	#0xa5:8, @(8:32, er1)	; Register plus 32-bit disp. operand
;;;	.word	0x015d
;;;	.word	0xc9a5
;;;	.long	8

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst-8, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	#0xa5, @word_dst
	beq	.Lnext8
	fail
.Lnext8:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_imm8_to_abs16:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:8, @aa:16
	mov.w	#0xa5:8, @word_dst:16	; 16-bit address-direct operand
;;;	.word	0x015d
;;;	.word	0x40a5
;;;	.word	@word_dst

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
	test_gr_a5a5 1		; (first, because on h8/300 we must use one
	test_gr_a5a5 2		; to examine the destination memory).
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	#0xa5, @word_dst
	beq	.Lnext9
	fail
.Lnext9:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_imm8_to_abs32:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:8, @aa:32
	mov.w	#0xa5:8, @word_dst:32	; 32-bit address-direct operand
;;;	.word	0x015d
;;;	.word	0x48a5
;;;	.long	@word_dst

	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
	test_neg_clear
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
	test_gr_a5a5 1		; (first, because on h8/300 we must use one
	test_gr_a5a5 2		; to examine the destination memory).
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	#0xa5, @word_dst
	beq	.Lnext10
	fail
.Lnext10:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_imm16_to_indirect:
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:16, @erd
	mov.l	#word_dst, er1
	mov.w	#0xdead:16, @er1	; Register indirect operand
;;;	.word	0x7974
;;;	.word	0xdead
;;;	.word	0x0100

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	#0xdead, @word_dst
	beq	.Lnext11
	fail
.Lnext11:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_imm16_to_postinc:		; post-increment from imm16 to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:16, @erd+
	mov.l	#word_dst, er1
	mov.w	#0xdead:16, @er1+	; Imm16, register post-incr operands.
;;;	.word	0x7974
;;;	.word	0xdead
;;;	.word	0x8100

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst+2, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	#0xdead, @word_dst
	beq	.Lnext12
	fail
.Lnext12:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_imm16_to_postdec:		; post-decrement from imm16 to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:16, @erd-
	mov.l	#word_dst, er1
	mov.w	#0xdead:16, @er1-	; Imm16, register post-decr operands.
;;;	.word	0x7974
;;;	.word	0xdead
;;;	.word	0xa100

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst-2, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	#0xdead, @word_dst
	beq	.Lnext13
	fail
.Lnext13:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_imm16_to_preinc:		; pre-increment from register to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:16, @+erd
	mov.l	#word_dst-2, er1
	mov.w	#0xdead:16, @+er1	; Imm16, register pre-incr operands
;;;	.word	0x7974
;;;	.word	0xdead
;;;	.word	0x9100

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7

	;; Now check the result of the move to memory.
	cmp.w	#0xdead, @word_dst
	beq	.Lnext14
	fail
.Lnext14:
	mov.w	#0, @word_dst	; zero it again for the next use.

mov_w_imm16_to_predec:		; pre-decrement from register to mem
	set_grs_a5a5		; Fill all general regs with a fixed pattern
	set_ccr_zero

	;; mov.w #xx:16, @-erd
	mov.l	#word_dst+2, er1
	mov.w	#0xdead:16, @-er1	; Imm16, register pre-decr operands
;;;	.word	0x7974
;;;	.word	0xdead
;;;	.word	0xb100

	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
	test_neg_set
	test_zero_clear
	test_ovf_clear
	test_carry_clear

	test_gr_a5a5 0		; Make sure other general regs not disturbed
	test_h_gr32	word_dst, er1
	test_gr_a5a5 2
	test_gr_a5a5 3
	test_gr_a5a5 4
	test_gr_a5a5 5
	test_gr_a5a5 6
	test_gr_a5a5 7