armemu.c

gdb-6.0 linux 下的调试工具

	      dest = DPImmRHS - LHS - !CFLAG;
	      WRITEDEST (dest);
	      break;

	    case 0x2f:		/* RSCS immed */
	      lhs = LHS;
	      rhs = DPImmRHS;
	      dest = rhs - lhs - !CFLAG;
	      if ((rhs >= lhs) || ((rhs | lhs) >> 31))
		{
		  ARMul_SubCarry (state, rhs, lhs, dest);
		  ARMul_SubOverflow (state, rhs, lhs, dest);
		}
	      else
		{
		  CLEARC;
		  CLEARV;
		}
	      WRITESDEST (dest);
	      break;

	    case 0x30:		/* TST immed */
	      UNDEF_Test;
	      break;

	    case 0x31:		/* TSTP immed */
	      if (DESTReg == 15)
		{
		  /* TSTP immed.  */
#ifdef MODE32
		  state->Cpsr = GETSPSR (state->Bank);
		  ARMul_CPSRAltered (state);
#else
		  temp = LHS & DPImmRHS;
		  SETR15PSR (temp);
#endif
		}
	      else
		{
		  /* TST immed.  */
		  DPSImmRHS;
		  dest = LHS & rhs;
		  ARMul_NegZero (state, dest);
		}
	      break;

	    case 0x32:		/* TEQ immed and MSR immed to CPSR */
	      if (DESTReg == 15)
		/* MSR immed to CPSR.  */
		ARMul_FixCPSR (state, instr, DPImmRHS);
	      else
		UNDEF_Test;
	      break;

	    case 0x33:		/* TEQP immed */
	      if (DESTReg == 15)
		{
		  /* TEQP immed.  */
#ifdef MODE32
		  state->Cpsr = GETSPSR (state->Bank);
		  ARMul_CPSRAltered (state);
#else
		  temp = LHS ^ DPImmRHS;
		  SETR15PSR (temp);
#endif
		}
	      else
		{
		  DPSImmRHS;	/* TEQ immed */
		  dest = LHS ^ rhs;
		  ARMul_NegZero (state, dest);
		}
	      break;

	    case 0x34:		/* CMP immed */
	      UNDEF_Test;
	      break;

	    case 0x35:		/* CMPP immed */
	      if (DESTReg == 15)
		{
		  /* CMPP immed.  */
#ifdef MODE32
		  state->Cpsr = GETSPSR (state->Bank);
		  ARMul_CPSRAltered (state);
#else
		  temp = LHS - DPImmRHS;
		  SETR15PSR (temp);
#endif
		  break;
		}
	      else
		{
		  /* CMP immed.  */
		  lhs = LHS;
		  rhs = DPImmRHS;
		  dest = lhs - rhs;
		  ARMul_NegZero (state, dest);

		  if ((lhs >= rhs) || ((rhs | lhs) >> 31))
		    {
		      ARMul_SubCarry (state, lhs, rhs, dest);
		      ARMul_SubOverflow (state, lhs, rhs, dest);
		    }
		  else
		    {
		      CLEARC;
		      CLEARV;
		    }
		}
	      break;

	    case 0x36:		/* CMN immed and MSR immed to SPSR */
	      if (DESTReg == 15)
		ARMul_FixSPSR (state, instr, DPImmRHS);
	      else
		UNDEF_Test;
	      break;

	    case 0x37:		/* CMNP immed.  */
	      if (DESTReg == 15)
		{
		  /* CMNP immed.  */
#ifdef MODE32
		  state->Cpsr = GETSPSR (state->Bank);
		  ARMul_CPSRAltered (state);
#else
		  temp = LHS + DPImmRHS;
		  SETR15PSR (temp);
#endif
		  break;
		}
	      else
		{
		  /* CMN immed.  */
		  lhs = LHS;
		  rhs = DPImmRHS;
		  dest = lhs + rhs;
		  ASSIGNZ (dest == 0);
		  if ((lhs | rhs) >> 30)
		    {
		      /* Possible C,V,N to set.  */
		      ASSIGNN (NEG (dest));
		      ARMul_AddCarry (state, lhs, rhs, dest);
		      ARMul_AddOverflow (state, lhs, rhs, dest);
		    }
		  else
		    {
		      CLEARN;
		      CLEARC;
		      CLEARV;
		    }
		}
	      break;

	    case 0x38:		/* ORR immed.  */
	      dest = LHS | DPImmRHS;
	      WRITEDEST (dest);
	      break;

	    case 0x39:		/* ORRS immed.  */
	      DPSImmRHS;
	      dest = LHS | rhs;
	      WRITESDEST (dest);
	      break;

	    case 0x3a:		/* MOV immed.  */
	      dest = DPImmRHS;
	      WRITEDEST (dest);
	      break;

	    case 0x3b:		/* MOVS immed.  */
	      DPSImmRHS;
	      WRITESDEST (rhs);
	      break;

	    case 0x3c:		/* BIC immed.  */
	      dest = LHS & ~DPImmRHS;
	      WRITEDEST (dest);
	      break;

	    case 0x3d:		/* BICS immed.  */
	      DPSImmRHS;
	      dest = LHS & ~rhs;
	      WRITESDEST (dest);
	      break;

	    case 0x3e:		/* MVN immed.  */
	      dest = ~DPImmRHS;
	      WRITEDEST (dest);
	      break;

	    case 0x3f:		/* MVNS immed.  */
	      DPSImmRHS;
	      WRITESDEST (~rhs);
	      break;


	      /* Single Data Transfer Immediate RHS Instructions.  */

	    case 0x40:		/* Store Word, No WriteBack, Post Dec, Immed.  */
	      lhs = LHS;
	      if (StoreWord (state, instr, lhs))
		LSBase = lhs - LSImmRHS;
	      break;

	    case 0x41:		/* Load Word, No WriteBack, Post Dec, Immed.  */
	      lhs = LHS;
	      if (LoadWord (state, instr, lhs))
		LSBase = lhs - LSImmRHS;
	      break;

	    case 0x42:		/* Store Word, WriteBack, Post Dec, Immed.  */
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      lhs = LHS;
	      temp = lhs - LSImmRHS;
	      state->NtransSig = LOW;
	      if (StoreWord (state, instr, lhs))
		LSBase = temp;
	      state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
	      break;

	    case 0x43:		/* Load Word, WriteBack, Post Dec, Immed.  */
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      lhs = LHS;
	      state->NtransSig = LOW;
	      if (LoadWord (state, instr, lhs))
		LSBase = lhs - LSImmRHS;
	      state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
	      break;

	    case 0x44:		/* Store Byte, No WriteBack, Post Dec, Immed.  */
	      lhs = LHS;
	      if (StoreByte (state, instr, lhs))
		LSBase = lhs - LSImmRHS;
	      break;

	    case 0x45:		/* Load Byte, No WriteBack, Post Dec, Immed.  */
	      lhs = LHS;
	      if (LoadByte (state, instr, lhs, LUNSIGNED))
		LSBase = lhs - LSImmRHS;
	      break;

	    case 0x46:		/* Store Byte, WriteBack, Post Dec, Immed.  */
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      lhs = LHS;
	      state->NtransSig = LOW;
	      if (StoreByte (state, instr, lhs))
		LSBase = lhs - LSImmRHS;
	      state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
	      break;

	    case 0x47:		/* Load Byte, WriteBack, Post Dec, Immed.  */
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      lhs = LHS;
	      state->NtransSig = LOW;
	      if (LoadByte (state, instr, lhs, LUNSIGNED))
		LSBase = lhs - LSImmRHS;
	      state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
	      break;

	    case 0x48:		/* Store Word, No WriteBack, Post Inc, Immed.  */
	      lhs = LHS;
	      if (StoreWord (state, instr, lhs))
		LSBase = lhs + LSImmRHS;
	      break;

	    case 0x49:		/* Load Word, No WriteBack, Post Inc, Immed.  */
	      lhs = LHS;
	      if (LoadWord (state, instr, lhs))
		LSBase = lhs + LSImmRHS;
	      break;

	    case 0x4a:		/* Store Word, WriteBack, Post Inc, Immed.  */
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      lhs = LHS;
	      state->NtransSig = LOW;
	      if (StoreWord (state, instr, lhs))
		LSBase = lhs + LSImmRHS;
	      state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
	      break;

	    case 0x4b:		/* Load Word, WriteBack, Post Inc, Immed.  */
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      lhs = LHS;
	      state->NtransSig = LOW;
	      if (LoadWord (state, instr, lhs))
		LSBase = lhs + LSImmRHS;
	      state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
	      break;

	    case 0x4c:		/* Store Byte, No WriteBack, Post Inc, Immed.  */
	      lhs = LHS;
	      if (StoreByte (state, instr, lhs))
		LSBase = lhs + LSImmRHS;
	      break;

	    case 0x4d:		/* Load Byte, No WriteBack, Post Inc, Immed.  */
	      lhs = LHS;
	      if (LoadByte (state, instr, lhs, LUNSIGNED))
		LSBase = lhs + LSImmRHS;
	      break;

	    case 0x4e:		/* Store Byte, WriteBack, Post Inc, Immed.  */
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      lhs = LHS;
	      state->NtransSig = LOW;
	      if (StoreByte (state, instr, lhs))
		LSBase = lhs + LSImmRHS;
	      state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
	      break;

	    case 0x4f:		/* Load Byte, WriteBack, Post Inc, Immed.  */
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      lhs = LHS;
	      state->NtransSig = LOW;
	      if (LoadByte (state, instr, lhs, LUNSIGNED))
		LSBase = lhs + LSImmRHS;
	      state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
	      break;


	    case 0x50:		/* Store Word, No WriteBack, Pre Dec, Immed.  */
	      (void) StoreWord (state, instr, LHS - LSImmRHS);
	      break;

	    case 0x51:		/* Load Word, No WriteBack, Pre Dec, Immed.  */
	      (void) LoadWord (state, instr, LHS - LSImmRHS);
	      break;

	    case 0x52:		/* Store Word, WriteBack, Pre Dec, Immed.  */
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      temp = LHS - LSImmRHS;
	      if (StoreWord (state, instr, temp))
		LSBase = temp;
	      break;

	    case 0x53:		/* Load Word, WriteBack, Pre Dec, Immed.  */
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      temp = LHS - LSImmRHS;
	      if (LoadWord (state, instr, temp))
		LSBase = temp;
	      break;

	    case 0x54:		/* Store Byte, No WriteBack, Pre Dec, Immed.  */
	      (void) StoreByte (state, instr, LHS - LSImmRHS);
	      break;

	    case 0x55:		/* Load Byte, No WriteBack, Pre Dec, Immed.  */
	      (void) LoadByte (state, instr, LHS - LSImmRHS, LUNSIGNED);
	      break;

	    case 0x56:		/* Store Byte, WriteBack, Pre Dec, Immed.  */
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      temp = LHS - LSImmRHS;
	      if (StoreByte (state, instr, temp))
		LSBase = temp;
	      break;

	    case 0x57:		/* Load Byte, WriteBack, Pre Dec, Immed.  */
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      temp = LHS - LSImmRHS;
	      if (LoadByte (state, instr, temp, LUNSIGNED))
		LSBase = temp;
	      break;

	    case 0x58:		/* Store Word, No WriteBack, Pre Inc, Immed.  */
	      (void) StoreWord (state, instr, LHS + LSImmRHS);
	      break;

	    case 0x59:		/* Load Word, No WriteBack, Pre Inc, Immed.  */
	      (void) LoadWord (state, instr, LHS + LSImmRHS);
	      break;

	    case 0x5a:		/* Store Word, WriteBack, Pre Inc, Immed.  */
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      temp = LHS + LSImmRHS;
	      if (StoreWord (state, instr, temp))
		LSBase = temp;
	      break;

	    case 0x5b:		/* Load Word, WriteBack, Pre Inc, Immed.  */
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      temp = LHS + LSImmRHS;
	      if (LoadWord (state, instr, temp))
		LSBase = temp;
	      break;

	    case 0x5c:		/* Store Byte, No WriteBack, Pre Inc, Immed.  */
	      (void) StoreByte (state, instr, LHS + LSImmRHS);
	      break;

	    case 0x5d:		/* Load Byte, No WriteBack, Pre Inc, Immed.  */
	      (void) LoadByte (state, instr, LHS + LSImmRHS, LUNSIGNED);
	      break;

	    case 0x5e:		/* Store Byte, WriteBack, Pre Inc, Immed.  */
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      temp = LHS + LSImmRHS;
	      if (StoreByte (state, instr, temp))
		LSBase = temp;
	      break;

	    case 0x5f:		/* Load Byte, WriteBack, Pre Inc, Immed.  */
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      temp = LHS + LSImmRHS;
	      if (LoadByte (state, instr, temp, LUNSIGNED))
		LSBase = temp;
	      break;


	      /* Single Data Transfer Register RHS Instructions.  */

	    case 0x60:		/* Store Word, No WriteBack, Post Dec, Reg.  */
	      if (BIT (4))
		{
		  ARMul_UndefInstr (state, instr);
		  break;
		}
	      UNDEF_LSRBaseEQOffWb;
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      UNDEF_LSRPCOffWb;
	      lhs = LHS;
	      if (StoreWord (state, instr, lhs))
		LSBase = lhs - LSRegRHS;
	      break;

	    case 0x61:		/* Load Word, No WriteBack, Post Dec, Reg.  */
	      if (BIT (4))
		{
		  ARMul_UndefInstr (state, instr);
		  break;
		}
	      UNDEF_LSRBaseEQOffWb;
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      UNDEF_LSRPCOffWb;
	      lhs = LHS;
	      temp = lhs - LSRegRHS;
	      if (LoadWord (state, instr, lhs))
		LSBase = temp;
	      break;

	    case 0x62:		/* Store Word, WriteBack, Post Dec, Reg.  */
	      if (BIT (4))
		{
		  ARMul_UndefInstr (state, instr);
		  break;
		}
	      UNDEF_LSRBaseEQOffWb;
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      UNDEF_LSRPCOffWb;
	      lhs = LHS;
	      state->NtransSig = LOW;
	      if (StoreWord (state, instr, lhs))
		LSBase = lhs - LSRegRHS;
	      state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
	      break;

	    case 0x63:		/* Load Word, WriteBack, Post Dec, Reg.  */
	      if (BIT (4))
		{
		  ARMul_UndefInstr (state, instr);
		  break;
		}
	      UNDEF_LSRBaseEQOffWb;
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      UNDEF_LSRPCOffWb;
	      lhs = LHS;
	      temp = lhs - LSRegRHS;
	      state->NtransSig = LOW;
	      if (LoadWord (state, instr, lhs))
		LSBase = temp;
	      state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
	      break;

	    case 0x64:		/* Store Byte, No WriteBack, Post Dec, Reg.  */
	      if (BIT (4))
		{
		  ARMul_UndefInstr (state, instr);
		  break;
		}
	      UNDEF_LSRBaseEQOffWb;
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      UNDEF_LSRPCOffWb;
	      lhs = LHS;
	      if (StoreByte (state, instr, lhs))
		LSBase = lhs - LSRegRHS;
	      break;

	    case 0x65:		/* Load Byte, No WriteBack, Post Dec, Reg.  */
	      if (BIT (4))
		{
		  ARMul_UndefInstr (state, instr);
		  break;
		}
	      UNDEF_LSRBaseEQOffWb;
	      UNDEF_LSRBaseEQDestWb;
	      UNDEF_LSRPCBaseWb;
	      UNDEF_LSRPCOffWb;