simops.c

gdb-6.0 linux 下的调试工具

/* bclr imm8, (abs32) */
void OP_FE010000 (insn, extension)
     unsigned long insn, extension;
{
  unsigned long temp;
  int z;

  temp = load_byte (((insn & 0xffff) << 16) | (extension >> 8));
  z = (temp & (extension & 0xff)) == 0;
  temp = temp & ~(extension & 0xff);
  store_byte (((insn & 0xffff) << 16) | (extension >> 8), temp);
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= (z ? PSW_Z : 0);
}

/* bclr imm8,(d8,an) */
void OP_FAF40000 (insn, extension)
     unsigned long insn, extension;
{
  unsigned long temp;
  int z;

  temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
                     + SEXT8 ((insn & 0xff00) >> 8)));
  z = (temp & (insn & 0xff)) == 0;
  temp = temp & ~(insn & 0xff);
  store_byte ((State.regs[REG_A0 + REG0_16 (insn)]
	       + SEXT8 ((insn & 0xff00) >> 8)), temp);
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= (z ? PSW_Z : 0);
}

/* asr dm, dn */
void OP_F2B0 (insn, extension)
     unsigned long insn, extension;
{
  long temp;
  int z, n, c;

  temp = State.regs[REG_D0 + REG0 (insn)];
  c = temp & 1;
  temp >>= State.regs[REG_D0 + REG1 (insn)];
  State.regs[REG_D0 + REG0 (insn)] = temp;
  z = (State.regs[REG_D0 + REG0 (insn)] == 0);
  n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}

/* asr imm8, dn */
void OP_F8C800 (insn, extension)
     unsigned long insn, extension;
{
  long temp;
  int z, n, c;

  temp = State.regs[REG_D0 + REG0_8 (insn)];
  c = temp & 1;
  temp >>= (insn & 0xff);
  State.regs[REG_D0 + REG0_8 (insn)] = temp;
  z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
  n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}

/* lsr dm, dn */
void OP_F2A0 (insn, extension)
     unsigned long insn, extension;
{
  int z, n, c;

  c = State.regs[REG_D0 + REG0 (insn)] & 1;
  State.regs[REG_D0 + REG0 (insn)]
    >>= State.regs[REG_D0 + REG1 (insn)];
  z = (State.regs[REG_D0 + REG0 (insn)] == 0);
  n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}

/* lsr imm8, dn */
void OP_F8C400 (insn, extension)
     unsigned long insn, extension;
{
  int z, n, c;

  c = State.regs[REG_D0 + REG0_8 (insn)] & 1;
  State.regs[REG_D0 + REG0_8 (insn)] >>=  (insn & 0xff);
  z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
  n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}

/* asl dm, dn */
void OP_F290 (insn, extension)
     unsigned long insn, extension;
{
  int n, z;

  State.regs[REG_D0 + REG0 (insn)]
    <<= State.regs[REG_D0 + REG1 (insn)];
  z = (State.regs[REG_D0 + REG0 (insn)] == 0);
  n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}

/* asl imm8, dn */
void OP_F8C000 (insn, extension)
     unsigned long insn, extension;
{
  int n, z;

  State.regs[REG_D0 + REG0_8 (insn)] <<= (insn & 0xff);
  z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
  n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}

/* asl2 dn */
void OP_54 (insn, extension)
     unsigned long insn, extension;
{
  int n, z;

  State.regs[REG_D0 + REG0 (insn)] <<= 2;
  z = (State.regs[REG_D0 + REG0 (insn)] == 0);
  n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}

/* ror dn */
void OP_F284 (insn, extension)
     unsigned long insn, extension;
{
  unsigned long value;
  int c,n,z;

  value = State.regs[REG_D0 + REG0 (insn)];
  c = (value & 0x1);

  value >>= 1;
  value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
  State.regs[REG_D0 + REG0 (insn)] = value;
  z = (value == 0);
  n = (value & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}

/* rol dn */
void OP_F280 (insn, extension)
     unsigned long insn, extension;
{
  unsigned long value;
  int c,n,z;

  value = State.regs[REG_D0 + REG0 (insn)];
  c = (value & 0x80000000) ? 1 : 0;

  value <<= 1;
  value |= ((PSW & PSW_C) != 0);
  State.regs[REG_D0 + REG0 (insn)] = value;
  z = (value == 0);
  n = (value & 0x80000000) != 0;
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}

/* beq label:8 */
void OP_C800 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
  if (PSW & PSW_Z)
    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
}

/* bne label:8 */
void OP_C900 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
  if (!(PSW & PSW_Z))
    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
}

/* bgt label:8 */
void OP_C100 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
  if (!((PSW & PSW_Z)
        || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
}

/* bge label:8 */
void OP_C200 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
  if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
}

/* ble label:8 */
void OP_C300 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
  if ((PSW & PSW_Z)
       || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
}

/* blt label:8 */
void OP_C000 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
  if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
}

/* bhi label:8 */
void OP_C500 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
  if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
}

/* bcc label:8 */
void OP_C600 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
  if (!(PSW & PSW_C))
    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
}

/* bls label:8 */
void OP_C700 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
  if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
}

/* bcs label:8 */
void OP_C400 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
  if (PSW & PSW_C)
    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
}

/* bvc label:8 */
void OP_F8E800 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if (!(PSW & PSW_V))
    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
}

/* bvs label:8 */
void OP_F8E900 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if (PSW & PSW_V)
    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
}

/* bnc label:8 */
void OP_F8EA00 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if (!(PSW & PSW_N))
    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
}

/* bns label:8 */
void OP_F8EB00 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 3 after we return, so
     we subtract two here to make things right.  */
  if (PSW & PSW_N)
    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
}

/* bra label:8 */
void OP_CA00 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 2 after we return, so
     we subtract two here to make things right.  */
  State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
}

/* leq */
void OP_D8 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 1 after we return, so
     we subtract one here to make things right.  */
  if (PSW & PSW_Z)
    State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
}

/* lne */
void OP_D9 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 1 after we return, so
     we subtract one here to make things right.  */
  if (!(PSW & PSW_Z))
    State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
}

/* lgt */
void OP_D1 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 1 after we return, so
     we subtract one here to make things right.  */
  if (!((PSW & PSW_Z)
        || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
    State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
}

/* lge */
void OP_D2 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 1 after we return, so
     we subtract one here to make things right.  */
  if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
    State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
}

/* lle */
void OP_D3 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 1 after we return, so
     we subtract one here to make things right.  */
  if ((PSW & PSW_Z)
       || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
    State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
}

/* llt */
void OP_D0 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 1 after we return, so
     we subtract one here to make things right.  */
  if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
    State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
}

/* lhi */
void OP_D5 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 1 after we return, so
     we subtract one here to make things right.  */
  if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
    State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
}

/* lcc */
void OP_D6 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 1 after we return, so
     we subtract one here to make things right.  */
  if (!(PSW & PSW_C))
    State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
}

/* lls */
void OP_D7 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 1 after we return, so
     we subtract one here to make things right.  */
  if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
    State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
}

/* lcs */
void OP_D4 (insn, extension)
     unsigned long insn, extension;
{
  /* The dispatching code will add 1 after we return, so
     we subtract one here to make things right.  */
  if (PSW & PSW_C)
    State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
}

/* lra */
void OP_DA (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
}

/* setlb */
void OP_DB (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_LIR] = load_mem_big (State.regs[REG_PC] + 1, 4);
  State.regs[REG_LAR] = State.regs[REG_PC] + 5;
}

/* jmp (an) */
void OP_F0F4 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2;
}

/* jmp label:16 */
void OP_CC0000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 3;
}

/* jmp label:32 */
void OP_DC000000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_PC] += (((insn & 0xffffff) << 8) + extension) - 5;
}

/* call label:16,reg_list,imm8 */
void OP_CD000000 (insn, extension)
     unsigned long insn, extension;
{
  unsigned int next_pc, sp;
  unsigned long mask;

  sp = State.regs[REG_SP];
  next_pc = State.regs[REG_PC] + 5;
  State.mem[sp] = next_pc & 0xff;
  State.mem[sp+1] = (next_pc & 0xff00) >> 8;
  State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
  State.mem[sp+3] = (next_pc & 0xff000000) >> 24;

  mask = insn & 0xff;

  if (mask & 0x80)
    {
      sp -= 4;
      store_word (sp, State.regs[REG_D0 + 2]);
    }

  if (mask & 0x40)
    {
      sp -= 4;
      store_word (sp, State.regs[REG_D0 + 3]);
    }

  if (mask & 0x20)
    {
      sp -= 4;
      store_word (sp, State.regs[REG_A0 + 2]);
    }

  if (mask & 0x10)
    {
      sp -= 4;
      store_word (sp, State.regs[REG_A0 + 3]);
    }

  if (mask & 0x8)
    {
      sp -= 4;
      store_word (sp, State.regs[REG_D0]);
      sp -= 4;
      store_word (sp, State.regs[REG_D0 + 1]);
      sp -= 4;
      store_word (sp, State.regs[REG_A0]);
      sp -= 4;
      store_word (sp, State.regs[REG_A0 + 1]);
      sp -= 4;
      store_word (sp, State.regs[REG_MDR]);
      sp -= 4;
      store_word (sp, State.regs[REG