simops.c

gdb-6.0 linux 下的调试工具

/* movbu (d32,am), dn */
void OP_FC400000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG1_16 (insn)]
    = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
		  + ((insn & 0xffff) << 16) + extension));
}

/* movbu (d8,sp), dn */
void OP_F8B800 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_8 (insn)]
    = load_byte ((State.regs[REG_SP] + (insn & 0xff)));
}

/* movbu (d16,sp), dn */
void OP_FAB80000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_16 (insn)]
    = load_byte ((State.regs[REG_SP] + (insn & 0xffff)));
}

/* movbu (d32,sp), dn */
void OP_FCB80000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_16 (insn)]
    = load_byte (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
}

/* movbu (di,am), dn */
void OP_F400 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_4 (insn)]
    = load_byte ((State.regs[REG_A0 + REG0 (insn)]
		  + State.regs[REG_D0 + REG1 (insn)]));
}

/* movbu (abs16), dn */
void OP_340000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_16 (insn)] = load_byte ((insn & 0xffff));
}

/* movbu (abs32), dn */
void OP_FCA80000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_16 (insn)]
    = load_byte ((((insn & 0xffff) << 16) + extension));
}

/* movbu dm, (an) */
void OP_F050 (insn, extension)
     unsigned long insn, extension;
{
  store_byte (State.regs[REG_A0 + REG0 (insn)],
	      State.regs[REG_D0 + REG1 (insn)]);
}

/* movbu dm, (d8,an) */
void OP_F85000 (insn, extension)
     unsigned long insn, extension;
{
  store_byte ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
	      State.regs[REG_D0 + REG1_8 (insn)]);
}

/* movbu dm, (d16,an) */
void OP_FA500000 (insn, extension)
     unsigned long insn, extension;
{
  store_byte ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
	      State.regs[REG_D0 + REG1_16 (insn)]);
}

/* movbu dm, (d32,an) */
void OP_FC500000 (insn, extension)
     unsigned long insn, extension;
{
  store_byte ((State.regs[REG_A0 + REG0_16 (insn)]
	       + ((insn & 0xffff) << 16) + extension),
	      State.regs[REG_D0 + REG1_16 (insn)]);
}

/* movbu dm, (d8,sp) */
void OP_F89200 (insn, extension)
     unsigned long insn, extension;
{
  store_byte (State.regs[REG_SP] + (insn & 0xff),
	      State.regs[REG_D0 + REG1_8 (insn)]);
}

/* movbu dm, (d16,sp) */
void OP_FA920000 (insn, extension)
     unsigned long insn, extension;
{
  store_byte (State.regs[REG_SP] + (insn & 0xffff),
	      State.regs[REG_D0 + REG1_16 (insn)]);
}

/* movbu dm (d32,sp) */
void OP_FC920000 (insn, extension)
     unsigned long insn, extension;
{
  store_byte (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
	      State.regs[REG_D0 + REG1_16 (insn)]);
}

/* movbu dm, (di,an) */
void OP_F440 (insn, extension)
     unsigned long insn, extension;
{
  store_byte ((State.regs[REG_A0 + REG0 (insn)]
	       + State.regs[REG_D0 + REG1 (insn)]),
	      State.regs[REG_D0 + REG0_4 (insn)]);
}

/* movbu dm, (abs16) */
void OP_20000 (insn, extension)
     unsigned long insn, extension;
{
  store_byte ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]);
}

/* movbu dm, (abs32) */
void OP_FC820000 (insn, extension)
     unsigned long insn, extension;
{
  store_byte ((((insn & 0xffff) << 16) + extension), State.regs[REG_D0 + REG1_16 (insn)]);
}

/* movhu (am), dn */
void OP_F060 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG1 (insn)]
    = load_half (State.regs[REG_A0 + REG0 (insn)]);
}

/* movhu (d8,am), dn */
void OP_F86000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG1_8 (insn)]
    = load_half ((State.regs[REG_A0 + REG0_8 (insn)]
		  + SEXT8 (insn & 0xff)));
}

/* movhu (d16,am), dn */
void OP_FA600000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG1_16 (insn)]
    = load_half ((State.regs[REG_A0 + REG0_16 (insn)]
		  + SEXT16 (insn & 0xffff)));
}

/* movhu (d32,am), dn */
void OP_FC600000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG1_16 (insn)]
    = load_half ((State.regs[REG_A0 + REG0_16 (insn)]
		  + ((insn & 0xffff) << 16) + extension));
}

/* movhu (d8,sp) dn */
void OP_F8BC00 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_8 (insn)]
    = load_half ((State.regs[REG_SP] + (insn & 0xff)));
}

/* movhu (d16,sp), dn */
void OP_FABC0000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_16 (insn)]
    = load_half ((State.regs[REG_SP] + (insn & 0xffff)));
}

/* movhu (d32,sp), dn */
void OP_FCBC0000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_16 (insn)]
    = load_half (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
}

/* movhu (di,am), dn */
void OP_F480 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_4 (insn)]
    = load_half ((State.regs[REG_A0 + REG0 (insn)]
		  + State.regs[REG_D0 + REG1 (insn)]));
}

/* movhu (abs16), dn */
void OP_380000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_16 (insn)] = load_half ((insn & 0xffff));
}

/* movhu (abs32), dn */
void OP_FCAC0000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_16 (insn)]
    = load_half ((((insn & 0xffff) << 16) + extension));
}

/* movhu dm, (an) */
void OP_F070 (insn, extension)
     unsigned long insn, extension;
{
  store_half (State.regs[REG_A0 + REG0 (insn)],
	      State.regs[REG_D0 + REG1 (insn)]);
}

/* movhu dm, (d8,an) */
void OP_F87000 (insn, extension)
     unsigned long insn, extension;
{
  store_half ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
	      State.regs[REG_D0 + REG1_8 (insn)]);
}

/* movhu dm, (d16,an) */
void OP_FA700000 (insn, extension)
     unsigned long insn, extension;
{
  store_half ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
	      State.regs[REG_D0 + REG1_16 (insn)]);
}

/* movhu dm, (d32,an) */
void OP_FC700000 (insn, extension)
     unsigned long insn, extension;
{
  store_half ((State.regs[REG_A0 + REG0_16 (insn)]
	       + ((insn & 0xffff) << 16) + extension),
	      State.regs[REG_D0 + REG1_16 (insn)]);
}

/* movhu dm,(d8,sp) */
void OP_F89300 (insn, extension)
     unsigned long insn, extension;
{
  store_half (State.regs[REG_SP] + (insn & 0xff),
	      State.regs[REG_D0 + REG1_8 (insn)]);
}

/* movhu dm,(d16,sp) */
void OP_FA930000 (insn, extension)
     unsigned long insn, extension;
{
  store_half (State.regs[REG_SP] + (insn & 0xffff),
	      State.regs[REG_D0 + REG1_16 (insn)]);
}

/* movhu dm,(d32,sp) */
void OP_FC930000 (insn, extension)
     unsigned long insn, extension;
{
  store_half (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
	      State.regs[REG_D0 + REG1_16 (insn)]);
}

/* movhu dm, (di,an) */
void OP_F4C0 (insn, extension)
     unsigned long insn, extension;
{
  store_half ((State.regs[REG_A0 + REG0 (insn)]
	       + State.regs[REG_D0 + REG1 (insn)]),
	      State.regs[REG_D0 + REG0_4 (insn)]);
}

/* movhu dm, (abs16) */
void OP_30000 (insn, extension)
     unsigned long insn, extension;
{
  store_half ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]);
}

/* movhu dm, (abs32) */
void OP_FC830000 (insn, extension)
     unsigned long insn, extension;
{
  store_half ((((insn & 0xffff) << 16) + extension), State.regs[REG_D0 + REG1_16 (insn)]);
}

/* ext dn */
void OP_F2D0 (insn, extension)
     unsigned long insn, extension;
{
  if (State.regs[REG_D0 + REG0 (insn)] & 0x80000000)
    State.regs[REG_MDR] = -1;
  else
    State.regs[REG_MDR] = 0;
}

/* extb dn */
void OP_10 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0 (insn)] = SEXT8 (State.regs[REG_D0 + REG0 (insn)]);
}

/* extbu dn */
void OP_14 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0 (insn)] &= 0xff;
}

/* exth dn */
void OP_18 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0 (insn)]
    = SEXT16 (State.regs[REG_D0 + REG0 (insn)]);
}

/* exthu dn */
void OP_1C (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0 (insn)] &= 0xffff;
}

/* movm (sp), reg_list */
void OP_CE00 (insn, extension)
     unsigned long insn, extension;
{
  unsigned long sp = State.regs[REG_SP];
  unsigned long mask;

  mask = insn & 0xff;

  if (mask & 0x8)
    {
      sp += 4;
      State.regs[REG_LAR] = load_word (sp);
      sp += 4;
      State.regs[REG_LIR] = load_word (sp);
      sp += 4;
      State.regs[REG_MDR] = load_word (sp);
      sp += 4;
      State.regs[REG_A0 + 1] = load_word (sp);
      sp += 4;
      State.regs[REG_A0] = load_word (sp);
      sp += 4;
      State.regs[REG_D0 + 1] = load_word (sp);
      sp += 4;
      State.regs[REG_D0] = load_word (sp);
      sp += 4;
    }

  if (mask & 0x10)
    {
      State.regs[REG_A0 + 3] = load_word (sp);
      sp += 4;
    }

  if (mask & 0x20)
    {
      State.regs[REG_A0 + 2] = load_word (sp);
      sp += 4;
    }

  if (mask & 0x40)
    {
      State.regs[REG_D0 + 3] = load_word (sp);
      sp += 4;
    }

  if (mask & 0x80)
    {
      State.regs[REG_D0 + 2] = load_word (sp);
      sp += 4;
    }

  /* And make sure to update the stack pointer.  */
  State.regs[REG_SP] = sp;
}

/* movm reg_list, (sp) */
void OP_CF00 (insn, extension)
     unsigned long insn, extension;
{
  unsigned long sp = State.regs[REG_SP];
  unsigned long mask;

  mask = insn & 0xff;

  if (mask & 0x80)
    {
      sp -= 4;
      store_word (sp, State.regs[REG_D0 + 2]);
    }

  if (mask & 0x40)
    {
      sp -= 4;
      store_word (sp, State.regs[REG_D0 + 3]);
    }

  if (mask & 0x20)
    {
      sp -= 4;
      store_word (sp, State.regs[REG_A0 + 2]);
    }

  if (mask & 0x10)
    {
      sp -= 4;
      store_word (sp, State.regs[REG_A0 + 3]);
    }

  if (mask & 0x8)
    {
      sp -= 4;
      store_word (sp, State.regs[REG_D0]);
      sp -= 4;
      store_word (sp, State.regs[REG_D0 + 1]);
      sp -= 4;
      store_word (sp, State.regs[REG_A0]);
      sp -= 4;
      store_word (sp, State.regs[REG_A0 + 1]);
      sp -= 4;
      store_word (sp, State.regs[REG_MDR]);
      sp -= 4;
      store_word (sp, State.regs[REG_LIR]);
      sp -= 4;
      store_word (sp, State.regs[REG_LAR]);
      sp -= 4;
    }

  /* And make sure to update the stack pointer.  */
  State.regs[REG_SP] = sp;
}

/* clr dn */
void OP_0 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG1 (insn)] = 0;

  PSW |= PSW_Z;
  PSW &= ~(PSW_V | PSW_C | PSW_N);
}

/* add dm,dn */
void OP_E0 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v;
  unsigned long reg1, reg2, value;

  reg1 = State.regs[REG_D0 + REG1 (insn)];
  reg2 = State.regs[REG_D0 + REG0 (insn)];
  value = reg1 + reg2;
  State.regs[REG_D0 + REG0 (insn)] = value;

  z = (value == 0);
  n = (value & 0x80000000);
  c = (value < reg1) || (value < reg2);
  v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
       && (reg2 & 0x80000000) != (value & 0x80000000));

  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
	  | (c ? PSW_C : 0) | (v ? PSW_V : 0));
}

/* add dm, an */
void OP_F160 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v;
  unsigned long reg1, reg2, value;

  reg1 = State.regs[REG_D0 + REG1 (insn)];
  reg2 = State.regs[REG_A0 + REG0 (insn)];
  value = reg1 + reg2;
  State.regs[REG_A0 + REG0 (insn)] = value;

  z = (value == 0);
  n = (value & 0x80000000);
  c = (value < reg1) || (value < reg2);
  v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
       && (reg2 & 0x80000000) != (value & 0x80000000));

  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
	  | (c ? PSW_C : 0) | (v ? PSW_V : 0));
}

/* add am, dn */
void OP_F150 (insn, extension)
     unsigned long insn, extension;
{
  int z, c, n, v;
  unsigned long reg1, reg2, value;

  reg1 = State.regs[REG_A0 + REG1 (insn)];
  reg2 = State.regs[REG_D0 + REG0 (insn)];
  value = reg1 + reg2;