simops.c

gdb-6.0 linux 下的调试工具

#include "config.h"

#include <signal.h>
#ifdef HAVE_UNISTD_H
#include <unistd.h>
#endif
#include "mn10300_sim.h"
#include "simops.h"
#include "sim-types.h"
#include "targ-vals.h"
#include "bfd.h"
#include <errno.h>
#include <sys/stat.h>
#include <sys/times.h>
#include <sys/time.h>

#define REG0(X) ((X) & 0x3)
#define REG1(X) (((X) & 0xc) >> 2)
#define REG0_4(X) (((X) & 0x30) >> 4)
#define REG0_8(X) (((X) & 0x300) >> 8)
#define REG1_8(X) (((X) & 0xc00) >> 10)
#define REG0_16(X) (((X) & 0x30000) >> 16)
#define REG1_16(X) (((X) & 0xc0000) >> 18)

/* mov imm8, dn */
void OP_8000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_8 (insn)] = SEXT8 (insn & 0xff);
}

/* mov dm, dn */
void OP_80 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)];
}

/* mov dm, an */
void OP_F1E0 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)];
}

/* mov am, dn */
void OP_F1D0 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)];
}

/* mov imm8, an */
void OP_9000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_A0 + REG0_8 (insn)] = insn & 0xff;
}

/* mov am, an */
void OP_90 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)];
}

/* mov sp, an */
void OP_3C (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_SP];
}

/* mov am, sp */
void OP_F2F0 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_SP] = State.regs[REG_A0 + REG1 (insn)];
}

/* mov psw, dn */
void OP_F2E4 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0 (insn)] = PSW;
}

/* mov dm, psw */
void OP_F2F3 (insn, extension)
     unsigned long insn, extension;
{
  PSW = State.regs[REG_D0 + REG1 (insn)];
}

/* mov mdr, dn */
void OP_F2E0 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_MDR];
}

/* mov dm, mdr */
void OP_F2F2 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_MDR] = State.regs[REG_D0 + REG1 (insn)];
}

/* mov (am), dn */
void OP_70 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG1 (insn)]
    = load_word (State.regs[REG_A0 + REG0 (insn)]);
}

/* mov (d8,am), dn */
void OP_F80000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG1_8 (insn)]
    = load_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)));
}

/* mov (d16,am), dn */
void OP_FA000000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG1_16 (insn)]
    = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
		  + SEXT16 (insn & 0xffff)));
}

/* mov (d32,am), dn */
void OP_FC000000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG1_16 (insn)]
    = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
		  + ((insn & 0xffff) << 16) + extension));
}

/* mov (d8,sp), dn */
void OP_5800 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_8 (insn)]
    = load_word (State.regs[REG_SP] + (insn & 0xff));
}

/* mov (d16,sp), dn */
void OP_FAB40000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_16 (insn)]
    = load_word (State.regs[REG_SP] + (insn & 0xffff));
}

/* mov (d32,sp), dn */
void OP_FCB40000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_16 (insn)]
    = load_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
}

/* mov (di,am), dn */
void OP_F300 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_4 (insn)]
    = load_word ((State.regs[REG_A0 + REG0 (insn)]
		  + State.regs[REG_D0 + REG1 (insn)]));
}

/* mov (abs16), dn */
void OP_300000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_16 (insn)] = load_word ((insn & 0xffff));
}

/* mov (abs32), dn */
void OP_FCA40000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG0_16 (insn)]
    = load_word ((((insn & 0xffff) << 16) + extension));
}

/* mov (am), an */
void OP_F000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_A0 + REG1 (insn)]
    = load_word (State.regs[REG_A0 + REG0 (insn)]);
}

/* mov (d8,am), an */
void OP_F82000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_A0 + REG1_8 (insn)]
    = load_word ((State.regs[REG_A0 + REG0_8 (insn)]
		  + SEXT8 (insn & 0xff)));
}

/* mov (d16,am), an */
void OP_FA200000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_A0 + REG1_16 (insn)]
    = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
		  + SEXT16 (insn & 0xffff)));
}

/* mov (d32,am), an */
void OP_FC200000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_A0 + REG1_16 (insn)]
    = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
		  + ((insn & 0xffff) << 16) + extension));
}

/* mov (d8,sp), an */
void OP_5C00 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_A0 + REG0_8 (insn)]
    = load_word (State.regs[REG_SP] + (insn & 0xff));
}

/* mov (d16,sp), an */
void OP_FAB00000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_A0 + REG0_16 (insn)]
    = load_word (State.regs[REG_SP] + (insn & 0xffff));
}

/* mov (d32,sp), an */
void OP_FCB00000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_A0 + REG0_16 (insn)]
    = load_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
}

/* mov (di,am), an */
void OP_F380 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_A0 + REG0_4 (insn)]
    = load_word ((State.regs[REG_A0 + REG0 (insn)]
		 + State.regs[REG_D0 + REG1 (insn)]));
}

/* mov (abs16), an */
void OP_FAA00000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_A0 + REG0_16 (insn)] = load_word ((insn & 0xffff));
}

/* mov (abs32), an */
void OP_FCA00000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_A0 + REG0_16 (insn)]
    = load_word ((((insn & 0xffff) << 16) + extension));
}

/* mov (d8,am), sp */
void OP_F8F000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_SP]
    = load_word ((State.regs[REG_A0 + REG0_8 (insn)]
		  + SEXT8 (insn & 0xff)));
}

/* mov dm, (an) */
void OP_60 (insn, extension)
     unsigned long insn, extension;
{
  store_word (State.regs[REG_A0 + REG0 (insn)],
	      State.regs[REG_D0 + REG1 (insn)]);
}

/* mov dm, (d8,an) */
void OP_F81000 (insn, extension)
     unsigned long insn, extension;
{
  store_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
	      State.regs[REG_D0 + REG1_8 (insn)]);
}

/* mov dm (d16,an) */
void OP_FA100000 (insn, extension)
     unsigned long insn, extension;
{
  store_word ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
	      State.regs[REG_D0 + REG1_16 (insn)]);
}

/* mov dm (d32,an) */
void OP_FC100000 (insn, extension)
     unsigned long insn, extension;
{
  store_word ((State.regs[REG_A0 + REG0_16 (insn)]
	       + ((insn & 0xffff) << 16) + extension),
	      State.regs[REG_D0 + REG1_16 (insn)]);
}

/* mov dm, (d8,sp) */
void OP_4200 (insn, extension)
     unsigned long insn, extension;
{
  store_word (State.regs[REG_SP] + (insn & 0xff),
	      State.regs[REG_D0 + REG1_8 (insn)]);
}

/* mov dm, (d16,sp) */
void OP_FA910000 (insn, extension)
     unsigned long insn, extension;
{
  store_word (State.regs[REG_SP] + (insn & 0xffff),
	      State.regs[REG_D0 + REG1_16 (insn)]);
}

/* mov dm, (d32,sp) */
void OP_FC910000 (insn, extension)
     unsigned long insn, extension;
{
  store_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
	      State.regs[REG_D0 + REG1_16 (insn)]);
}

/* mov dm, (di,an) */
void OP_F340 (insn, extension)
     unsigned long insn, extension;
{
  store_word ((State.regs[REG_A0 + REG0 (insn)]
	       + State.regs[REG_D0 + REG1 (insn)]),
	      State.regs[REG_D0 + REG0_4 (insn)]);
}

/* mov dm, (abs16) */
void OP_10000 (insn, extension)
     unsigned long insn, extension;
{
  store_word ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]);
}

/* mov dm, (abs32) */
void OP_FC810000 (insn, extension)
     unsigned long insn, extension;
{
  store_word ((((insn & 0xffff) << 16) + extension), 
	      State.regs[REG_D0 + REG1_16 (insn)]);
}

/* mov am, (an) */
void OP_F010 (insn, extension)
     unsigned long insn, extension;
{
  store_word (State.regs[REG_A0 + REG0 (insn)],
	      State.regs[REG_A0 + REG1 (insn)]);
}

/* mov am, (d8,an) */
void OP_F83000 (insn, extension)
     unsigned long insn, extension;
{
  store_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
	      State.regs[REG_A0 + REG1_8 (insn)]);
}

/* mov am, (d16,an) */
void OP_FA300000 (insn, extension)
     unsigned long insn, extension;
{
  store_word ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
	      State.regs[REG_A0 + REG1_16 (insn)]);
}

/* mov am, (d32,an) */
void OP_FC300000 (insn, extension)
     unsigned long insn, extension;
{
  store_word ((State.regs[REG_A0 + REG0_16 (insn)]
	       + ((insn & 0xffff) << 16) + extension),
	      State.regs[REG_A0 + REG1_16 (insn)]);
}

/* mov am, (d8,sp) */
void OP_4300 (insn, extension)
     unsigned long insn, extension;
{
  store_word (State.regs[REG_SP] + (insn & 0xff),
	      State.regs[REG_A0 + REG1_8 (insn)]);
}

/* mov am, (d16,sp) */
void OP_FA900000 (insn, extension)
     unsigned long insn, extension;
{
  store_word (State.regs[REG_SP] + (insn & 0xffff),
	      State.regs[REG_A0 + REG1_16 (insn)]);
}

/* mov am, (d32,sp) */
void OP_FC900000 (insn, extension)
     unsigned long insn, extension;
{
  store_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
	      State.regs[REG_A0 + REG1_16 (insn)]);
}

/* mov am, (di,an) */
void OP_F3C0 (insn, extension)
     unsigned long insn, extension;
{
  store_word ((State.regs[REG_A0 + REG0 (insn)]
	       + State.regs[REG_D0 + REG1 (insn)]),
	      State.regs[REG_A0 + REG0_4 (insn)]);
}

/* mov am, (abs16) */
void OP_FA800000 (insn, extension)
     unsigned long insn, extension;
{
  store_word ((insn & 0xffff), State.regs[REG_A0 + REG1_16 (insn)]);
}

/* mov am, (abs32) */
void OP_FC800000 (insn, extension)
     unsigned long insn, extension;
{
  store_word ((((insn & 0xffff) << 16) + extension), State.regs[REG_A0 + REG1_16 (insn)]);
}

/* mov sp, (d8,an) */
void OP_F8F400 (insn, extension)
     unsigned long insn, extension;
{
  store_word (State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff),
	      State.regs[REG_SP]);
}

/* mov imm16, dn */
void OP_2C0000 (insn, extension)
     unsigned long insn, extension;
{
  unsigned long value;

  value = SEXT16 (insn & 0xffff);
  State.regs[REG_D0 + REG0_16 (insn)] = value;
}

/* mov imm32,dn */
void OP_FCCC0000 (insn, extension)
     unsigned long insn, extension;
{
  unsigned long value;

  value = ((insn & 0xffff) << 16) + extension;
  State.regs[REG_D0 + REG0_16 (insn)] = value;
}

/* mov imm16, an */
void OP_240000 (insn, extension)
     unsigned long insn, extension;
{
  unsigned long value;

  value = insn & 0xffff;
  State.regs[REG_A0 + REG0_16 (insn)] = value;
}

/* mov imm32, an */
void OP_FCDC0000 (insn, extension)
     unsigned long insn, extension;
{
  unsigned long value;

  value = ((insn & 0xffff) << 16) + extension;
  State.regs[REG_A0 + REG0_16 (insn)] = value;
}

/* movbu (am), dn */
void OP_F040 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG1 (insn)]
    = load_byte (State.regs[REG_A0 + REG0 (insn)]);
}

/* movbu (d8,am), dn */
void OP_F84000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG1_8 (insn)]
    = load_byte ((State.regs[REG_A0 + REG0_8 (insn)]
		  + SEXT8 (insn & 0xff)));
}

/* movbu (d16,am), dn */
void OP_FA400000 (insn, extension)
     unsigned long insn, extension;
{
  State.regs[REG_D0 + REG1_16 (insn)]
    = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
		  + SEXT16 (insn & 0xffff)));
}