interp.c

gdb-6.0 linux 下的调试工具

	  case 0x40:
	  case 0x41:
	  case 0x44:
	  case 0x45:
	  case 0x48:
	  case 0x49:
	  case 0x4c:
	  case 0x4d:
	  case 0x50:
	  case 0x51:
	  case 0x52:
	  case 0x53:
	  case 0x54:
	  case 0x55:
	  case 0x56:
	  case 0x57:
	  case 0x60:
	  case 0x61:
	  case 0x62:
	  case 0x63:
	  case 0x64:
	  case 0x65:
	  case 0x66:
	  case 0x67:
	  case 0x68:
	  case 0x69:
	  case 0x6a:
	  case 0x6b:
	  case 0x6c:
	  case 0x6d:
	  case 0x6e:
	  case 0x6f:
	  case 0x70:
	  case 0x71:
	  case 0x72:
	  case 0x73:
	  case 0x74:
	  case 0x75:
	  case 0x76:
	  case 0x77:
	  case 0x78:
	  case 0x79:
	  case 0x7a:
	  case 0x7b:
	  case 0x7c:
	  case 0x7d:
	  case 0x7e:
	  case 0x7f:
	  case 0xcb:
	  case 0xd0:
	  case 0xd1:
	  case 0xd2:
	  case 0xd3:
	  case 0xd4:
	  case 0xd5:
	  case 0xd6:
	  case 0xd7:
	  case 0xd8:
	  case 0xd9:
	  case 0xda:
	  case 0xdb:
	  case 0xe0:
	  case 0xe1:
	  case 0xe2:
	  case 0xe3:
	  case 0xe4:
	  case 0xe5:
	  case 0xe6:
	  case 0xe7:
	  case 0xe8:
	  case 0xe9:
	  case 0xea:
	  case 0xeb:
	  case 0xec:
	  case 0xed:
	  case 0xee:
	  case 0xef:
	  case 0xff:
	    insn = (inst >> 8) & 0xff;
	    extension = 0;
	    dispatch (insn, extension, 1);
	    break;

	  /* Special cases where dm == dn is used to encode a different
	     instruction.  */
	  case 0x80:
	  case 0x85:
	  case 0x8a:
	  case 0x8f:
	  case 0x90:
	  case 0x95:
	  case 0x9a:
	  case 0x9f:
	  case 0xa0:
	  case 0xa5:
	  case 0xaa:
	  case 0xaf:
	  case 0xb0:
	  case 0xb5:
	  case 0xba:
	  case 0xbf:
	    insn = inst;
	    extension = 0;
	    dispatch (insn, extension, 2);
	    break;

	  case 0x81:
	  case 0x82:
	  case 0x83:
	  case 0x84:
	  case 0x86:
	  case 0x87:
	  case 0x88:
	  case 0x89:
	  case 0x8b:
	  case 0x8c:
	  case 0x8d:
	  case 0x8e:
	  case 0x91:
	  case 0x92:
	  case 0x93:
	  case 0x94:
	  case 0x96:
	  case 0x97:
	  case 0x98:
	  case 0x99:
	  case 0x9b:
	  case 0x9c:
	  case 0x9d:
	  case 0x9e:
	  case 0xa1:
	  case 0xa2:
	  case 0xa3:
	  case 0xa4:
	  case 0xa6:
	  case 0xa7:
	  case 0xa8:
	  case 0xa9:
	  case 0xab:
	  case 0xac:
	  case 0xad:
	  case 0xae:
	  case 0xb1:
	  case 0xb2:
	  case 0xb3:
	  case 0xb4:
	  case 0xb6:
	  case 0xb7:
	  case 0xb8:
	  case 0xb9:
	  case 0xbb:
	  case 0xbc:
	  case 0xbd:
	  case 0xbe:
	    insn = (inst >> 8) & 0xff;
	    extension = 0;
	  dispatch (insn, extension, 1);
	  break;

	  /* The two byte instructions.  */
	  case 0x20:
	  case 0x21:
	  case 0x22:
	  case 0x23:
	  case 0x28:
	  case 0x29:
	  case 0x2a:
	  case 0x2b:
	  case 0x42:
	  case 0x43:
	  case 0x46:
	  case 0x47:
	  case 0x4a:
	  case 0x4b:
	  case 0x4e:
	  case 0x4f:
	  case 0x58:
	  case 0x59:
	  case 0x5a:
	  case 0x5b:
	  case 0x5c:
	  case 0x5d:
	  case 0x5e:
	  case 0x5f:
	  case 0xc0:
	  case 0xc1:
	  case 0xc2:
	  case 0xc3:
	  case 0xc4:
	  case 0xc5:
	  case 0xc6:
	  case 0xc7:
	  case 0xc8:
	  case 0xc9:
	  case 0xca:
	  case 0xce:
	  case 0xcf:
	  case 0xf0:
	  case 0xf1:
	  case 0xf2:
	  case 0xf3:
	  case 0xf4:
	  case 0xf5:
	  case 0xf6:
	    insn = inst;
	    extension = 0;
	    dispatch (insn, extension, 2);
	    break;

	  /* The three byte insns with a 16bit operand in little endian
	     format.  */
	  case 0x01:
	  case 0x02:
	  case 0x03:
	  case 0x05:
	  case 0x06:
	  case 0x07:
	  case 0x09:
	  case 0x0a:
	  case 0x0b:
	  case 0x0d:
	  case 0x0e:
	  case 0x0f:
	  case 0x24:
	  case 0x25:
	  case 0x26:
	  case 0x27:
	  case 0x2c:
	  case 0x2d:
	  case 0x2e:
	  case 0x2f:
	  case 0x30:
	  case 0x31:
	  case 0x32:
	  case 0x33:
	  case 0x34:
	  case 0x35:
	  case 0x36:
	  case 0x37:
	  case 0x38:
	  case 0x39:
	  case 0x3a:
	  case 0x3b:
	  case 0xcc:
	    insn = load_byte (PC);
	    insn <<= 16;
	    insn |= load_half (PC + 1);
	    extension = 0;
	    dispatch (insn, extension, 3);
	    break;

	  /* The three byte insns without 16bit operand.  */
	  case 0xde:
	  case 0xdf:
	  case 0xf8:
	  case 0xf9:
	    insn = load_mem_big (PC, 3);
	    extension = 0;
	    dispatch (insn, extension, 3);
	    break;
	  
	  /* Four byte insns.  */
	  case 0xfa:
	  case 0xfb:
	    if ((inst & 0xfffc) == 0xfaf0
		|| (inst & 0xfffc) == 0xfaf4
		|| (inst & 0xfffc) == 0xfaf8)
	      insn = load_mem_big (PC, 4);
	    else
	      {
		insn = inst;
		insn <<= 16;
		insn |= load_half (PC + 2);
		extension = 0;
	      }
	    dispatch (insn, extension, 4);
	    break;

	  /* Five byte insns.  */
	  case 0xcd:
	    insn = load_byte (PC);
	    insn <<= 24;
	    insn |= (load_half (PC + 1) << 8);
	    insn |= load_byte (PC + 3);
	    extension = load_byte (PC + 4);
	    dispatch (insn, extension, 5);
	    break;

	  case 0xdc:
	    insn = load_byte (PC);
	    insn <<= 24;
	    extension = load_word (PC + 1);
	    insn |= (extension & 0xffffff00) >> 8;
	    extension &= 0xff;
	    dispatch (insn, extension, 5);
	    break;
	
	  /* Six byte insns.  */
	  case 0xfc:
	  case 0xfd:
	    insn = (inst << 16);
	    extension = load_word (PC + 2);
	    insn |= ((extension & 0xffff0000) >> 16);
	    extension &= 0xffff;
	    dispatch (insn, extension, 6);
	    break;
	    
	  case 0xdd:
	    insn = load_byte (PC) << 24;
	    extension = load_word (PC + 1);
	    insn |= ((extension >> 8) & 0xffffff);
	    extension = (extension & 0xff) << 16;
	    extension |= load_byte (PC + 5) << 8;
	    extension |= load_byte (PC + 6);
	    dispatch (insn, extension, 7);
	    break;

	  case 0xfe:
	    insn = inst << 16;
	    extension = load_word (PC + 2);
	    insn |= ((extension >> 16) & 0xffff);
	    extension <<= 8;
	    extension &= 0xffff00;
	    extension |= load_byte (PC + 6);
	    dispatch (insn, extension, 7);
	    break;

	  default:
	    abort ();
	}
    }
  while (!State.exception);

#ifdef HASH_STAT
  {
    int i;
    for (i = 0; i < MAX_HASH; i++)
      {
	 struct hash_entry *h;
	 h = &hash_table[i];

	 printf("hash 0x%x:\n", i);

	 while (h)
	   {
	     printf("h->opcode = 0x%x, count = 0x%x\n", h->opcode, h->count);
	     h = h->next;
	   }

	 printf("\n\n");
      }
    fflush (stdout);
  }
#endif

}

int
sim_trace (sd)
     SIM_DESC sd;
{
#ifdef DEBUG
  mn10300_debug = DEBUG;
#endif
  sim_resume (sd, 0, 0);
  return 1;
}

void
sim_info (sd, verbose)
     SIM_DESC sd;
     int verbose;
{
  (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_info\n");
}

SIM_RC
sim_create_inferior (sd, abfd, argv, env)
     SIM_DESC sd;
     struct bfd *abfd;
     char **argv;
     char **env;
{
  if (abfd != NULL)
    PC = bfd_get_start_address (abfd);
  else
    PC = 0;
  return SIM_RC_OK;
}

void
sim_set_callbacks (p)
     host_callback *p;
{
  mn10300_callback = p;
}

/* All the code for exiting, signals, etc needs to be revamped.

   This is enough to get c-torture limping though.  */

void
sim_stop_reason (sd, reason, sigrc)
     SIM_DESC sd;
     enum sim_stop *reason;
     int *sigrc;
{
  if (State.exited)
    *reason = sim_exited;
  else
    *reason = sim_stopped;

  if (State.exception == SIGQUIT)
    *sigrc = 0;
  else
    *sigrc = State.exception;
}

int
sim_read (sd, addr, buffer, size)
     SIM_DESC sd;
     SIM_ADDR addr;
     unsigned char *buffer;
     int size;
{
  int i;
  for (i = 0; i < size; i++)
    buffer[i] = load_byte (addr + i);

  return size;
} 

void
sim_do_command (sd, cmd)
     SIM_DESC sd;
     char *cmd;
{
  (*mn10300_callback->printf_filtered) (mn10300_callback, "\"%s\" is not a valid mn10300 simulator command.\n", cmd);
}

SIM_RC
sim_load (sd, prog, abfd, from_tty)
     SIM_DESC sd;
     char *prog;
     bfd *abfd;
     int from_tty;
{
  extern bfd *sim_load_file (); /* ??? Don't know where this should live.  */
  bfd *prog_bfd;

  prog_bfd = sim_load_file (sd, myname, mn10300_callback, prog, abfd,
			    sim_kind == SIM_OPEN_DEBUG,
			    0, sim_write);
  if (prog_bfd == NULL)
    return SIM_RC_FAIL;
  if (abfd == NULL)
    bfd_close (prog_bfd);
  return SIM_RC_OK;
} 
#endif  /* not WITH_COMMON */


#if WITH_COMMON

/* For compatibility */
SIM_DESC simulator;

/* These default values correspond to expected usage for the chip.  */

SIM_DESC
sim_open (kind, cb, abfd, argv)
     SIM_OPEN_KIND kind;
     host_callback *cb;
     struct bfd *abfd;
     char **argv;