changelog

gdb-6.0 linux 下的调试工具

	correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
	(MULT): Actually pass the third register...

1999-09-03  Mark Salter  <[e-mail]>

	* interp.c (sim_open): Added more memory aliases for additional
	hardware being touched by cygmon on jmr3904 board.

Thu Sep  2 18:15:53 1999  Andrew Cagney  <[e-mail]>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Tue Jul 27 16:36:51 1999  Andrew Cagney  <[e-mail]>

	* interp.c (sim_store_register): Handle case where client - GDB -
 	specifies that a 4 byte register is 8 bytes in size.
	(sim_fetch_register): Ditto.
	
1999-07-14  Frank Ch. Eigler  <[e-mail]>

	Implement "sim firmware" option, inspired by jimb's version of 1998-01.
	* interp.c (firmware_option_p): New global flag: "sim firmware" given.
	(idt_monitor_base): Base address for IDT monitor traps.
	(pmon_monitor_base): Ditto for PMON.
	(lsipmon_monitor_base): Ditto for LSI PMON.
	(MONITOR_BASE, MONITOR_SIZE): Removed macros.
	(mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
	(sim_firmware_command): New function.
	(mips_option_handler): Call it for OPTION_FIRMWARE.
	(sim_open): Allocate memory for idt_monitor region.  If "--board"
	option was given, add no monitor by default.  Add BREAK hooks only if
	monitors are also there.
	
Mon Jul 12 00:02:27 1999  Andrew Cagney  <[e-mail]>

	* interp.c (sim_monitor): Flush output before reading input.

Sun Jul 11 19:28:11 1999  Andrew Cagney  <[e-mail]>

	* tconfig.in (SIM_HANDLES_LMA): Always define.

Thu Jul  8 16:06:59 1999  Andrew Cagney  <[e-mail]>

	From Mark Salter <[e-mail]>:
	* interp.c (BOARD_BSP): Define.  Add to list of possible boards.
	(sim_open): Add setup for BSP board.

Wed Jul  7 12:45:58 1999  Andrew Cagney  <[e-mail]>

	* mips.igen (MULT, MULTU): Add syntax for two operand version.
	(DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 	them as unimplemented.

1999-05-08  Felix Lee  <[e-mail]>

	* configure: Regenerated to track ../common/aclocal.m4 changes.
	
1999-04-21  Frank Ch. Eigler  <[e-mail]>

	* mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.

Thu Apr 15 14:15:17 1999  Andrew Cagney  <[e-mail]>

	* configure.in: Any mips64vr5*-*-* target should have
 	-DTARGET_ENABLE_FR=1.
	(default_endian): Any mips64vr*el-*-* target should default to
	LITTLE_ENDIAN.
	* configure: Re-generate.

1999-02-19  Gavin Romig-Koch  <[e-mail]>

	* mips.igen (ldl): Extend from _16_, not 32.

Wed Jan 27 18:51:38 1999  Andrew Cagney  <[e-mail]>

	* interp.c (sim_store_register): Force registers written to by GDB
 	into an un-interpreted state.

1999-02-05  Frank Ch. Eigler  <[e-mail]>

	* dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 	CPU, start periodic background I/O polls.
	(tx3904sio_poll): New function: periodic I/O poller. 

1998-12-30  Frank Ch. Eigler  <[e-mail]>

	* mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
	
Tue Dec 29 16:03:53 1998  Rainer Orth  <[e-mail]>

	* configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 	case statement.

1998-12-29  Frank Ch. Eigler  <[e-mail]>
	
	* interp.c (sim_open): Allocate jm3904 memory in smaller chunks. 
	(load_word): Call SIM_CORE_SIGNAL hook on error.
	(signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
	starting.  For exception dispatching, pass PC instead of NULL_CIA.
	(decode_coproc): Use COP0_BADVADDR to store faulting address.
	* sim-main.h (COP0_BADVADDR): Define. 
	(SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
	(SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
	(_sim_cpu): Add exc_* fields to store register value snapshots.	
	* mips.igen (*): Replace memory-related SignalException* calls
	with references to SIM_CORE_SIGNAL hook.
	
	* dv-tx3904irc.c (tx3904irc_port_event): printf format warning
	fix.
	* sim-main.c (*): Minor warning cleanups.
	
1998-12-24  Gavin Romig-Koch  <[e-mail]>

	* m16.igen (DADDIU5): Correct type-o.

Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>

	* mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 	variables.

Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>

	* Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 	to include path.
	(interp.o): Add dependency on itable.h
	(oengine.c, gencode): Delete remaining references.
	(BUILT_SRC_FROM_GEN): Clean up.
	
1998-12-16  Gavin Romig-Koch  <[e-mail]>
	
	* vr4run.c: New.
	* Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
	tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
	tmp-run-hack) : New.
	* m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
	DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX): 
	Drop the "64" qualifier to get the HACK generator working.
	Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
	* mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
	qualifier to get the hack generator working.
	(do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
	(DSLL): Use do_dsll.
	(DSLLV): Use do_dsllv.
	(DSRA): Use do_dsra.
	(DSRL): Use do_dsrl.
	(DSRLV): Use do_dsrlv.
	(BC1): Move *vr4100 to get the HACK generator working.
	(CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to 
	get the HACK generator working.
	(MACC) Rename to get the HACK generator working.
	(DMACC,MACCS,DMACCS): Add the 64.
	
1998-12-12  Gavin Romig-Koch  <[e-mail]>

	* mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
	* sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
	
1998-12-11  Gavin Romig-Koch  <[e-mail]>

    * mips/interp.c (DEBUG): Cleanups.

1998-12-10  Frank Ch. Eigler  <[e-mail]>

	* dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
	(tx3904sio_tickle): fflush after a stdout character output.
	
1998-12-03  Frank Ch. Eigler  <[e-mail]>

	* interp.c (sim_close): Uninstall modules.

Wed Nov 25 13:41:03 1998  Andrew Cagney  <[e-mail]>

	* sim-main.h, interp.c (sim_monitor): Change to global
 	function.

Wed Nov 25 17:33:24 1998  Andrew Cagney  <[e-mail]>

	* configure.in (vr4100): Only include vr4100 instructions in
 	simulator.
	* configure: Re-generate.
	* m16.igen (*): Tag all mips16 instructions as also being vr4100.

Mon Nov 23 18:20:36 1998  Andrew Cagney  <[e-mail]>

	* Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
	* sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 	true alternative.

	* configure.in (sim_default_gen, sim_use_gen): Replace with
 	sim_gen.
	(--enable-sim-igen): Delete config option. Always using IGEN.
	* configure: Re-generate.
	
	* Makefile.in (gencode): Kill, kill, kill.
	* gencode.c: Ditto.
	
Mon Nov 23 18:07:36 1998  Andrew Cagney  <[e-mail]>

	* configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 	bit mips16 igen simulator.
	* configure: Re-generate.

	* mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 	as part of vr4100 ISA.
	* vr.igen: Mark all instructions as 64 bit only.

Mon Nov 23 17:07:37 1998  Andrew Cagney  <[e-mail]>

	* interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 	Pacify GCC.

Mon Nov 23 13:23:40 1998  Andrew Cagney  <[e-mail]>

	* configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 	mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
	* configure: Re-generate.

	* m16.igen (BREAK): Define breakpoint instruction.
	(JALX32): Mark instruction as mips16 and not r3900.
	* mips.igen (C.cond.fmt): Fix typo in instruction format.

	* sim-main.h (PENDING_FILL): Wrap C statements in do/while.

Sat Nov  7 09:54:38 1998  Andrew Cagney  <[e-mail]>

	* gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 	insn as a debug breakpoint.

	* sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 	pending.slot_size.
	(PENDING_SCHED): Clean up trace statement.
	(PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
	(PENDING_FILL): Delay write by only one cycle.
	(PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.

	* sim-main.c (pending_tick): Clean up trace statements. Add trace
 	of pending writes.
	(pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 	32 & 64.
	(pending_tick): Move incrementing of index to FOR statement.
	(pending_tick): Only update PENDING_OUT after a write has occured.
	
	* configure.in: Add explicit mips-lsi-* target.  Use gencode to
 	build simulator.
	* configure: Re-generate.
	
	* interp.c (sim_engine_run OLD): Delete explicit call to
 	PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
	
Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <[e-mail]>

	* dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
	interrupt level number to match changed SignalExceptionInterrupt
	macro.

Fri Oct  9 18:02:25 1998  Doug Evans  <[e-mail]>

	* interp.c: #include "itable.h" if WITH_IGEN.
	(get_insn_name): New function.
	(sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
	* sim-main.h (MAX_INSNS,INSN_NAME): Delete.

Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <[e-mail]>

	* configure: Rebuilt to inhale new common/aclocal.m4.

Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <[e-mail]>

	* dv-tx3904sio.c: Include sim-assert.h.

Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <[e-mail]>

	* dv-tx3904sio.c: New file: tx3904 serial I/O module.
	* configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
	Reorganize target-specific sim-hardware checks.
	* configure: rebuilt.
	* interp.c (sim_open): For tx39 target boards, set
	OPERATING_ENVIRONMENT, add tx3904sio devices.
	* tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
	ROM executables.  Install dv-sockser into sim-modules list.
	
	* dv-tx3904irc.c: Compiler warning clean-up.
	* dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
	frequent hw-trace messages.

Fri Jul 31 18:14:16 1998  Andrew Cagney  <[e-mail]>

	* vr.igen (MulAcc): Identify as a vr4100 specific function.

Sat Jul 25 16:03:14 1998  Andrew Cagney  <[e-mail]>

	* Makefile.in (IGEN_INCLUDE): Add vr.igen.

	* vr.igen: New file.
	(MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
	* mips.igen: Define vr4100 model. Include vr.igen.
Mon Jun 29 09:21:07 1998  Gavin Koch  <[e-mail]>

	* mips.igen (check_mf_hilo): Correct check.

Wed Jun 17 12:20:49 1998  Andrew Cagney  <[e-mail]>

	* sim-main.h (interrupt_event): Add prototype.

	* dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 	register_ptr, register_value.
	(deliver_tx3904tmr_tick): Fix types passed to printf fmt.

	* sim-main.h (tracefh): Make extern.

Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <[e-mail]>

	* dv-tx3904tmr.c: Deschedule timer event after dispatching.
	Reduce unnecessarily high timer event frequency.  
	* dv-tx3904cpu.c: Ditto for interrupt event.
	
Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <[e-mail]>

	* interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 	to allay warnings.
	(interrupt_event): Made non-static.
	
	* dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 	interchange of configuration values for external vs. internal
 	clock dividers.
	
Tue Jun  9 12:46:24 1998  Ian Carmichael  <[e-mail]>

	* mips.igen (BREAK): Moved code to here for 
	simulator-reserved break instructions.
	* gencode.c (build_instruction): Ditto.
	* interp.c (signal_exception): Code moved from here.  Non-
	reserved instructions now use exception vector, rather 
	than halting sim.
	* sim-main.h: Moved magic constants to here.

Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <[e-mail]>

	* dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 	register upon non-zero interrupt event level, clear upon zero
 	event value.
	* dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
	by passing zero event value.
	(*_io_{read,write}_buffer): Endianness fixes.
	* dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
	(deliver_*_tick): Reduce sim event interval to 75% of count interval.

	* interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
	serial I/O and timer module at base address 0xFFFF0000.
	
Tue Jun  9 11:52:29 1998  Gavin Koch  <[e-mail]>

	* mips.igen (SWC1) : Correct the handling of ReverseEndian 
	and BigEndianCPU.

Tue Jun  9 11:40:57 1998  Gavin Koch  <[e-mail]>

	* configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
	parts.
	* configure: Update.

Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <[e-mail]>

	* dv-tx3904tmr.c: New file - implements tx3904 timer.
	* dv-tx3904{irc,cpu}.c: Mild reformatting.
	* configure.in: Include tx3904tmr in hw_device list.
	* configure: Rebuilt.
	* interp.c (sim_open): Instantiate three timer instances.
	Fix address typo of tx3904irc instance.

Tue Jun  2 15:48:02 1998  Ian Carmichael  <[e-mail]>

	* interp.c (signal_exception): SystemCall exception now uses
	the exception vector.

Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <[e-mail]>