i960.h

gdb-6.0 linux 下的调试工具

	{ 0x82000000,	"stob",		I_BASE,	MEM1,	2, { R,  M,  0 } },
	{ 0x84000000,	"bx",		I_BASE,	MEM1,	1, { M,  0,  0 } },
	{ 0x85000000,	"balx",		I_BASE,	MEM1,	2, { M,  R,  0 } },
	{ 0x86000000,	"callx",	I_BASE,	MEM1,	1, { M,  0,  0 } },
	{ 0x88000000,	"ldos",		I_BASE,	MEM2,	2, { M,  R,  0 } },
	{ 0x8a000000,	"stos",		I_BASE,	MEM2,	2, { R,  M,  0 } },
	{ 0x8c000000,	"lda",		I_BASE,	MEM1,	2, { M,  R,  0 } },
	{ 0x90000000,	"ld",		I_BASE,	MEM4,	2, { M,  R,  0 } },
	{ 0x92000000,	"st",		I_BASE,	MEM4,	2, { R,  M,  0 } },
	{ 0x98000000,	"ldl",		I_BASE,	MEM8,	2, { M,  R2, 0 } },
	{ 0x9a000000,	"stl",		I_BASE,	MEM8,	2, { R2, M,  0 } },
	{ 0xa0000000,	"ldt",		I_BASE,	MEM12,	2, { M,  R4, 0 } },
	{ 0xa2000000,	"stt",		I_BASE,	MEM12,	2, { R4, M,  0 } },
	{ 0xb0000000,	"ldq",		I_BASE,	MEM16,	2, { M,  R4, 0 } },
	{ 0xb2000000,	"stq",		I_BASE,	MEM16,	2, { R4, M,  0 } },
	{ 0xc0000000,	"ldib",		I_BASE,	MEM1,	2, { M,  R,  0 } },
	{ 0xc2000000,	"stib",		I_BASE,	MEM1,	2, { R,  M,  0 } },
	{ 0xc8000000,	"ldis",		I_BASE,	MEM2,	2, { M,  R,  0 } },
	{ 0xca000000,	"stis",		I_BASE,	MEM2,	2, { R,  M,  0 } },

	{ R_3(0x580),	"notbit",	I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x581),	"and",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x582),	"andnot",	I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x583),	"setbit",	I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x584),	"notand",	I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x586),	"xor",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x587),	"or",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x588),	"nor",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x589),	"xnor",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_2D(0x58a),	"not",		I_BASE,	REG,	2, { RSL,RS, 0 } },
	{ R_3(0x58b),	"ornot",	I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x58c),	"clrbit",	I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x58d),	"notor",	I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x58e),	"nand",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x58f),	"alterbit",	I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x590),	"addo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x591),	"addi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x592),	"subo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x593),	"subi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x598),	"shro",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x59a),	"shrdi",	I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x59b),	"shri",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x59c),	"shlo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x59d),	"rotate",	I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x59e),	"shli",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_2(0x5a0),	"cmpo",		I_BASE,	REG,	2, { RSL,RSL, 0 } },
	{ R_2(0x5a1),	"cmpi",		I_BASE,	REG,	2, { RSL,RSL, 0 } },
	{ R_2(0x5a2),	"concmpo",	I_BASE,	REG,	2, { RSL,RSL, 0 } },
	{ R_2(0x5a3),	"concmpi",	I_BASE,	REG,	2, { RSL,RSL, 0 } },
	{ R_3(0x5a4),	"cmpinco",	I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x5a5),	"cmpinci",	I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x5a6),	"cmpdeco",	I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x5a7),	"cmpdeci",	I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_2(0x5ac),	"scanbyte",	I_BASE,	REG,	2, { RSL,RSL, 0 } },
	{ R_2(0x5ae),	"chkbit",	I_BASE,	REG,	2, { RSL,RSL, 0 } },
	{ R_3(0x5b0),	"addc",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x5b2),	"subc",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_2D(0x5cc),	"mov",		I_BASE,	REG,	2, { RSL,RS, 0 } },
	{ R_2D(0x5dc),	"movl",		I_BASE,	REG,	2, { RL2,R2, 0 } },
	{ R_2D(0x5ec),	"movt",		I_BASE,	REG,	2, { RL4,R4, 0 } },
	{ R_2D(0x5fc),	"movq",		I_BASE,	REG,	2, { RL4,R4, 0 } },
	{ R_3(0x610),	"atmod",	I_BASE,	REG,	3, { RS, RSL,R } },
	{ R_3(0x612),	"atadd",	I_BASE,	REG,	3, { RS, RSL,RS } },
	{ R_2D(0x640),	"spanbit",	I_BASE,	REG,	2, { RSL,RS, 0 } },
	{ R_2D(0x641),	"scanbit",	I_BASE,	REG,	2, { RSL,RS, 0 } },
	{ R_3(0x645),	"modac",	I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x650),	"modify",	I_BASE,	REG,	3, { RSL,RSL,R } },
	{ R_3(0x651),	"extract",	I_BASE,	REG,	3, { RSL,RSL,R } },
	{ R_3(0x654),	"modtc",	I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x655),	"modpc",	I_BASE,	REG,	3, { RSL,RSL,R } },
	{ R_1(0x660),	"calls",	I_BASE,	REG,	1, { RSL, 0, 0 } },
	{ R_0(0x66b),	"mark",		I_BASE,	REG,	0, { 0, 0, 0 }	},
	{ R_0(0x66c),	"fmark",	I_BASE,	REG,	0, { 0, 0, 0 }	},
	{ R_0(0x66d),	"flushreg",	I_BASE,	REG,	0, { 0, 0, 0 }	},
	{ R_0(0x66f),	"syncf",	I_BASE,	REG,	0, { 0, 0, 0 }	},
	{ R_3(0x670),	"emul",		I_BASE,	REG,	3, { RSL,RSL,R2 } },
	{ R_3(0x671),	"ediv",		I_BASE,	REG,	3, { RSL,RL2,RS } },
	{ R_2D(0x672),	"cvtadr",	I_CASIM,REG, 	2, { RL, R2, 0 } },
	{ R_3(0x701),	"mulo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x708),	"remo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x70b),	"divo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x741),	"muli",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x748),	"remi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x749),	"modi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x74b),	"divi",		I_BASE,	REG,	3, { RSL,RSL,RS } },

	/* Floating-point instructions */

	{ R_2D(0x674),	"cvtir",	I_FP,	REG,	2, { RL, F, 0 } },
	{ R_2D(0x675),	"cvtilr",	I_FP,	REG,	2, { RL, F, 0 } },
	{ R_3(0x676),	"scalerl",	I_FP,	REG,	3, { RL, FL2,F2 } },
	{ R_3(0x677),	"scaler",	I_FP,	REG,	3, { RL, FL, F } },
	{ R_3(0x680),	"atanr",	I_FP,	REG,	3, { FL, FL, F } },
	{ R_3(0x681),	"logepr",	I_FP,	REG,	3, { FL, FL, F } },
	{ R_3(0x682),	"logr",		I_FP,	REG,	3, { FL, FL, F } },
	{ R_3(0x683),	"remr",		I_FP,	REG,	3, { FL, FL, F } },
	{ R_2(0x684),	"cmpor",	I_FP,	REG,	2, { FL, FL, 0 } },
	{ R_2(0x685),	"cmpr",		I_FP,	REG,	2, { FL, FL, 0 } },
	{ R_2D(0x688),	"sqrtr",	I_FP,	REG,	2, { FL, F, 0 } },
	{ R_2D(0x689),	"expr",		I_FP,	REG,	2, { FL, F, 0 } },
	{ R_2D(0x68a),	"logbnr",	I_FP,	REG,	2, { FL, F, 0 } },
	{ R_2D(0x68b),	"roundr",	I_FP,	REG,	2, { FL, F, 0 } },
	{ R_2D(0x68c),	"sinr",		I_FP,	REG,	2, { FL, F, 0 } },
	{ R_2D(0x68d),	"cosr",		I_FP,	REG,	2, { FL, F, 0 } },
	{ R_2D(0x68e),	"tanr",		I_FP,	REG,	2, { FL, F, 0 } },
	{ R_1(0x68f),	"classr",	I_FP,	REG,	1, { FL, 0, 0 }	},
	{ R_3(0x690),	"atanrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
	{ R_3(0x691),	"logeprl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
	{ R_3(0x692),	"logrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
	{ R_3(0x693),	"remrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
	{ R_2(0x694),	"cmporl",	I_FP,	REG,	2, { FL2,FL2, 0 } },
	{ R_2(0x695),	"cmprl",	I_FP,	REG,	2, { FL2,FL2, 0 } },
	{ R_2D(0x698),	"sqrtrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
	{ R_2D(0x699),	"exprl",	I_FP,	REG,	2, { FL2,F2, 0 } },
	{ R_2D(0x69a),	"logbnrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
	{ R_2D(0x69b),	"roundrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
	{ R_2D(0x69c),	"sinrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
	{ R_2D(0x69d),	"cosrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
	{ R_2D(0x69e),	"tanrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
	{ R_1(0x69f),	"classrl",	I_FP,	REG,	1, { FL2, 0, 0 } },
	{ R_2D(0x6c0),	"cvtri",	I_FP,	REG,	2, { FL, R, 0 } },
	{ R_2D(0x6c1),	"cvtril",	I_FP,	REG,	2, { FL, R2, 0 } },
	{ R_2D(0x6c2),	"cvtzri",	I_FP,	REG,	2, { FL, R, 0 } },
	{ R_2D(0x6c3),	"cvtzril",	I_FP,	REG,	2, { FL, R2, 0 } },
	{ R_2D(0x6c9),	"movr",		I_FP,	REG,	2, { FL, F, 0 } },
	{ R_2D(0x6d9),	"movrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
	{ R_2D(0x6e1),	"movre",	I_FP,	REG,	2, { FL4,F4, 0 } },
	{ R_3(0x6e2),	"cpysre",	I_FP,	REG,	3, { FL4,FL4,F4 } },
	{ R_3(0x6e3),	"cpyrsre",	I_FP,	REG,	3, { FL4,FL4,F4 } },
	{ R_3(0x78b),	"divr",		I_FP,	REG,	3, { FL, FL, F } },
	{ R_3(0x78c),	"mulr",		I_FP,	REG,	3, { FL, FL, F } },
	{ R_3(0x78d),	"subr",		I_FP,	REG,	3, { FL, FL, F } },
	{ R_3(0x78f),	"addr",		I_FP,	REG,	3, { FL, FL, F } },
	{ R_3(0x79b),	"divrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
	{ R_3(0x79c),	"mulrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
	{ R_3(0x79d),	"subrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
	{ R_3(0x79f),	"addrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },

	/* These are the floating point branch instructions.  Each actually
	 * generates 2 branch instructions:  the first a CTRL instruction with
	 * the indicated opcode, and the second a 'bno'.
	 */

	{ 0x12000000,	"brue",		I_FP,	FBRA, 	1, { 0, 0, 0 }	},
	{ 0x11000000,	"brug",		I_FP,	FBRA, 	1, { 0, 0, 0 }	},
	{ 0x13000000,	"bruge",	I_FP,	FBRA, 	1, { 0, 0, 0 }	},
	{ 0x14000000,	"brul",		I_FP,	FBRA, 	1, { 0, 0, 0 }	},
	{ 0x16000000,	"brule",	I_FP,	FBRA, 	1, { 0, 0, 0 }	},
	{ 0x15000000,	"brulg",	I_FP,	FBRA, 	1, { 0, 0, 0 }	},


	/* Decimal instructions */

	{ R_3(0x642),	"daddc",	I_DEC,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x643),	"dsubc",	I_DEC,	REG,	3, { RSL,RSL,RS } },
	{ R_2D(0x644),	"dmovt",	I_DEC,	REG,	2, { RSL,RS, 0 } },


	/* KX extensions */

	{ R_2(0x600),	"synmov",	I_KX,	REG,	2, { R,  R, 0 } },
	{ R_2(0x601),	"synmovl",	I_KX,	REG,	2, { R,  R, 0 } },
	{ R_2(0x602),	"synmovq",	I_KX,	REG,	2, { R,  R, 0 } },
	{ R_2D(0x615),	"synld",	I_KX,	REG,	2, { R,  R, 0 } },


	/* MC extensions */

	{ R_3(0x603),	"cmpstr",	I_MIL,	REG,	3, { R,  R,  RL } },
	{ R_3(0x604),	"movqstr",	I_MIL,	REG,	3, { R,  R,  RL } },
	{ R_3(0x605),	"movstr",	I_MIL,	REG,	3, { R,  R,  RL } },
	{ R_2D(0x613),	"inspacc",	I_MIL,	REG,	2, { R,  R, 0 } },
	{ R_2D(0x614),	"ldphy",	I_MIL,	REG,	2, { R,  R, 0 } },
	{ R_3(0x617),	"fill",		I_MIL,	REG,	3, { R,  RL, RL } },
	{ R_2D(0x646),	"condrec",	I_MIL,	REG,	2, { R,  R, 0 } },
	{ R_2D(0x656),	"receive",	I_MIL,	REG,	2, { R,  R, 0 } },
	{ R_3(0x662),	"send",		I_MIL,	REG,	3, { R,  RL, R } },
	{ R_1(0x663),	"sendserv",	I_MIL,	REG,	1, { R, 0, 0 }	},
	{ R_1(0x664),	"resumprcs",	I_MIL,	REG,	1, { R, 0, 0 }	},
	{ R_1(0x665),	"schedprcs",	I_MIL,	REG,	1, { R, 0, 0 }	},
	{ R_0(0x666),	"saveprcs",	I_MIL,	REG,	0, { 0, 0, 0 }	},
	{ R_1(0x668),	"condwait",	I_MIL,	REG,	1, { R, 0, 0 }	},
	{ R_1(0x669),	"wait",		I_MIL,	REG,	1, { R, 0, 0 }	},
	{ R_1(0x66a),	"signal",	I_MIL,	REG,	1, { R, 0, 0 }	},
	{ R_1D(0x673),	"ldtime",	I_MIL,	REG,	1, { R2, 0, 0 }	},


	/* CX extensions */

	{ R_3(0x5d8),	"eshro",	I_CX2,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x630),	"sdma",		I_CX,	REG,	3, { RSL,RSL,RL } },
	{ R_3(0x631),	"udma",		I_CX,	REG,	0, { 0, 0, 0 }	},
	{ R_3(0x659),	"sysctl",	I_CX2,	REG,	3, { RSL,RSL,RL } },


	/* Jx extensions.  */
	{ R_3(0x780),	"addono",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x790),	"addog",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7a0),	"addoe",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7b0),	"addoge",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7c0),	"addol",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7d0),	"addone",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7e0),	"addole",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7f0),	"addoo",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x781),	"addino",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x791),	"addig",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7a1),	"addie",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7b1),	"addige",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7c1),	"addil",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7d1),	"addine",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7e1),	"addile",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7f1),	"addio",	I_JX,	REG,	3, { RSL,RSL,RS } },

	{ R_2D(0x5ad),	"bswap",	I_JX,	REG,	2, { RSL, RS, 0 } },

	{ R_2(0x594),	"cmpob",	I_JX,	REG,	2, { RSL,RSL, 0 } },
	{ R_2(0x595),	"cmpib",	I_JX,	REG,	2, { RSL,RSL, 0 } },
	{ R_2(0x596),	"cmpos",	I_JX,	REG,	2, { RSL,RSL, 0 } },
	{ R_2(0x597),	"cmpis",	I_JX,	REG,	2, { RSL,RSL, 0 } },

	{ R_3(0x784),	"selno",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x794),	"selg",		I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7a4),	"sele",		I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7b4),	"selge",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7c4),	"sell",		I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7d4),	"selne",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7e4),	"selle",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7f4),	"selo",		I_JX,	REG,	3, { RSL,RSL,RS } },

	{ R_3(0x782),	"subono",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x792),	"subog",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7a2),	"suboe",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7b2),	"suboge",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7c2),	"subol",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7d2),	"subone",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7e2),	"subole",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7f2),	"suboo",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x783),	"subino",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x793),	"subig",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7a3),	"subie",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7b3),	"subige",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7c3),	"subil",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7d3),	"subine",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7e3),	"subile",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_3(0x7f3),	"subio",	I_JX,	REG,	3, { RSL,RSL,RS } },

	{ R_3(0x65c),	"dcctl",	I_JX,	REG,	3, { RSL,RSL,RL } },
	{ R_3(0x65b),	"icctl",	I_JX,	REG,	3, { RSL,RSL,RS } },
	{ R_2D(0x658),	"intctl",	I_JX,	REG,	2, { RSL, RS, 0 } },
	{ R_0(0x5b4),	"intdis",	I_JX,	REG,	0, {   0,  0, 0 } },
	{ R_0(0x5b5),	"inten",	I_JX,	REG,	0, {   0,  0, 0 } },
	{ R_0(0x65d),	"halt",		I_JX,	REG,	1, { RSL,  0, 0 } },

	/* Hx extensions.  */
	{ 0xac000000,	"dcinva",	I_HX,	MEM1,	1, {   M,  0, 0 } },

	/* END OF TABLE */

	{ 0,		NULL,		0,	0,	0, { 0, 0, 0 }	}
};

 /* end of i960-opcode.h */