reloc.texi

gdb-6.0 linux 下的调试工具

@deffn {} BFD_RELOC_390_PLT64
64 bit PC relative PLT address.
@end deffn
@deffn {} BFD_RELOC_390_GOTENT
32 bit rel. offset to GOT entry.
@end deffn
@deffn {} BFD_RELOC_390_GOTOFF64
64 bit offset to GOT.
@end deffn
@deffn {} BFD_RELOC_390_GOTPLT12
12-bit offset to symbol-entry within GOT, with PLT handling.
@end deffn
@deffn {} BFD_RELOC_390_GOTPLT16
16-bit offset to symbol-entry within GOT, with PLT handling.
@end deffn
@deffn {} BFD_RELOC_390_GOTPLT32
32-bit offset to symbol-entry within GOT, with PLT handling.
@end deffn
@deffn {} BFD_RELOC_390_GOTPLT64
64-bit offset to symbol-entry within GOT, with PLT handling.
@end deffn
@deffn {} BFD_RELOC_390_GOTPLTENT
32-bit rel. offset to symbol-entry within GOT, with PLT handling.
@end deffn
@deffn {} BFD_RELOC_390_PLTOFF16
16-bit rel. offset from the GOT to a PLT entry.
@end deffn
@deffn {} BFD_RELOC_390_PLTOFF32
32-bit rel. offset from the GOT to a PLT entry.
@end deffn
@deffn {} BFD_RELOC_390_PLTOFF64
64-bit rel. offset from the GOT to a PLT entry.
@end deffn
@deffn {} BFD_RELOC_390_TLS_LOAD
@deffnx {} BFD_RELOC_390_TLS_GDCALL
@deffnx {} BFD_RELOC_390_TLS_LDCALL
@deffnx {} BFD_RELOC_390_TLS_GD32
@deffnx {} BFD_RELOC_390_TLS_GD64
@deffnx {} BFD_RELOC_390_TLS_GOTIE12
@deffnx {} BFD_RELOC_390_TLS_GOTIE32
@deffnx {} BFD_RELOC_390_TLS_GOTIE64
@deffnx {} BFD_RELOC_390_TLS_LDM32
@deffnx {} BFD_RELOC_390_TLS_LDM64
@deffnx {} BFD_RELOC_390_TLS_IE32
@deffnx {} BFD_RELOC_390_TLS_IE64
@deffnx {} BFD_RELOC_390_TLS_IEENT
@deffnx {} BFD_RELOC_390_TLS_LE32
@deffnx {} BFD_RELOC_390_TLS_LE64
@deffnx {} BFD_RELOC_390_TLS_LDO32
@deffnx {} BFD_RELOC_390_TLS_LDO64
@deffnx {} BFD_RELOC_390_TLS_DTPMOD
@deffnx {} BFD_RELOC_390_TLS_DTPOFF
@deffnx {} BFD_RELOC_390_TLS_TPOFF
s390 tls relocations.
@end deffn
@deffn {} BFD_RELOC_IP2K_FR9
Scenix IP2K - 9-bit register number / data address
@end deffn
@deffn {} BFD_RELOC_IP2K_BANK
Scenix IP2K - 4-bit register/data bank number
@end deffn
@deffn {} BFD_RELOC_IP2K_ADDR16CJP
Scenix IP2K - low 13 bits of instruction word address
@end deffn
@deffn {} BFD_RELOC_IP2K_PAGE3
Scenix IP2K - high 3 bits of instruction word address
@end deffn
@deffn {} BFD_RELOC_IP2K_LO8DATA
@deffnx {} BFD_RELOC_IP2K_HI8DATA
@deffnx {} BFD_RELOC_IP2K_EX8DATA
Scenix IP2K - ext/low/high 8 bits of data address
@end deffn
@deffn {} BFD_RELOC_IP2K_LO8INSN
@deffnx {} BFD_RELOC_IP2K_HI8INSN
Scenix IP2K - low/high 8 bits of instruction word address
@end deffn
@deffn {} BFD_RELOC_IP2K_PC_SKIP
Scenix IP2K - even/odd PC modifier to modify snb pcl.0
@end deffn
@deffn {} BFD_RELOC_IP2K_TEXT
Scenix IP2K - 16 bit word address in text section.
@end deffn
@deffn {} BFD_RELOC_IP2K_FR_OFFSET
Scenix IP2K - 7-bit sp or dp offset
@end deffn
@deffn {} BFD_RELOC_VPE4KMATH_DATA
@deffnx {} BFD_RELOC_VPE4KMATH_INSN
Scenix VPE4K coprocessor - data/insn-space addressing
@end deffn
@deffn {} BFD_RELOC_VTABLE_INHERIT
@deffnx {} BFD_RELOC_VTABLE_ENTRY
These two relocations are used by the linker to determine which of
the entries in a C++ virtual function table are actually used.  When
the --gc-sections option is given, the linker will zero out the entries
that are not used, so that the code for those functions need not be
included in the output.

VTABLE_INHERIT is a zero-space relocation used to describe to the
linker the inheritence tree of a C++ virtual function table.  The
relocation's symbol should be the parent class' vtable, and the
relocation should be located at the child vtable.

VTABLE_ENTRY is a zero-space relocation that describes the use of a
virtual function table entry.  The reloc's symbol should refer to the
table of the class mentioned in the code.  Off of that base, an offset
describes the entry that is being used.  For Rela hosts, this offset
is stored in the reloc's addend.  For Rel hosts, we are forced to put
this offset in the reloc's section offset.
@end deffn
@deffn {} BFD_RELOC_IA64_IMM14
@deffnx {} BFD_RELOC_IA64_IMM22
@deffnx {} BFD_RELOC_IA64_IMM64
@deffnx {} BFD_RELOC_IA64_DIR32MSB
@deffnx {} BFD_RELOC_IA64_DIR32LSB
@deffnx {} BFD_RELOC_IA64_DIR64MSB
@deffnx {} BFD_RELOC_IA64_DIR64LSB
@deffnx {} BFD_RELOC_IA64_GPREL22
@deffnx {} BFD_RELOC_IA64_GPREL64I
@deffnx {} BFD_RELOC_IA64_GPREL32MSB
@deffnx {} BFD_RELOC_IA64_GPREL32LSB
@deffnx {} BFD_RELOC_IA64_GPREL64MSB
@deffnx {} BFD_RELOC_IA64_GPREL64LSB
@deffnx {} BFD_RELOC_IA64_LTOFF22
@deffnx {} BFD_RELOC_IA64_LTOFF64I
@deffnx {} BFD_RELOC_IA64_PLTOFF22
@deffnx {} BFD_RELOC_IA64_PLTOFF64I
@deffnx {} BFD_RELOC_IA64_PLTOFF64MSB
@deffnx {} BFD_RELOC_IA64_PLTOFF64LSB
@deffnx {} BFD_RELOC_IA64_FPTR64I
@deffnx {} BFD_RELOC_IA64_FPTR32MSB
@deffnx {} BFD_RELOC_IA64_FPTR32LSB
@deffnx {} BFD_RELOC_IA64_FPTR64MSB
@deffnx {} BFD_RELOC_IA64_FPTR64LSB
@deffnx {} BFD_RELOC_IA64_PCREL21B
@deffnx {} BFD_RELOC_IA64_PCREL21BI
@deffnx {} BFD_RELOC_IA64_PCREL21M
@deffnx {} BFD_RELOC_IA64_PCREL21F
@deffnx {} BFD_RELOC_IA64_PCREL22
@deffnx {} BFD_RELOC_IA64_PCREL60B
@deffnx {} BFD_RELOC_IA64_PCREL64I
@deffnx {} BFD_RELOC_IA64_PCREL32MSB
@deffnx {} BFD_RELOC_IA64_PCREL32LSB
@deffnx {} BFD_RELOC_IA64_PCREL64MSB
@deffnx {} BFD_RELOC_IA64_PCREL64LSB
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB
@deffnx {} BFD_RELOC_IA64_SEGREL32MSB
@deffnx {} BFD_RELOC_IA64_SEGREL32LSB
@deffnx {} BFD_RELOC_IA64_SEGREL64MSB
@deffnx {} BFD_RELOC_IA64_SEGREL64LSB
@deffnx {} BFD_RELOC_IA64_SECREL32MSB
@deffnx {} BFD_RELOC_IA64_SECREL32LSB
@deffnx {} BFD_RELOC_IA64_SECREL64MSB
@deffnx {} BFD_RELOC_IA64_SECREL64LSB
@deffnx {} BFD_RELOC_IA64_REL32MSB
@deffnx {} BFD_RELOC_IA64_REL32LSB
@deffnx {} BFD_RELOC_IA64_REL64MSB
@deffnx {} BFD_RELOC_IA64_REL64LSB
@deffnx {} BFD_RELOC_IA64_LTV32MSB
@deffnx {} BFD_RELOC_IA64_LTV32LSB
@deffnx {} BFD_RELOC_IA64_LTV64MSB
@deffnx {} BFD_RELOC_IA64_LTV64LSB
@deffnx {} BFD_RELOC_IA64_IPLTMSB
@deffnx {} BFD_RELOC_IA64_IPLTLSB
@deffnx {} BFD_RELOC_IA64_COPY
@deffnx {} BFD_RELOC_IA64_LTOFF22X
@deffnx {} BFD_RELOC_IA64_LDXMOV
@deffnx {} BFD_RELOC_IA64_TPREL14
@deffnx {} BFD_RELOC_IA64_TPREL22
@deffnx {} BFD_RELOC_IA64_TPREL64I
@deffnx {} BFD_RELOC_IA64_TPREL64MSB
@deffnx {} BFD_RELOC_IA64_TPREL64LSB
@deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22
@deffnx {} BFD_RELOC_IA64_DTPMOD64MSB
@deffnx {} BFD_RELOC_IA64_DTPMOD64LSB
@deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22
@deffnx {} BFD_RELOC_IA64_DTPREL14
@deffnx {} BFD_RELOC_IA64_DTPREL22
@deffnx {} BFD_RELOC_IA64_DTPREL64I
@deffnx {} BFD_RELOC_IA64_DTPREL32MSB
@deffnx {} BFD_RELOC_IA64_DTPREL32LSB
@deffnx {} BFD_RELOC_IA64_DTPREL64MSB
@deffnx {} BFD_RELOC_IA64_DTPREL64LSB
@deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22
Intel IA64 Relocations.
@end deffn
@deffn {} BFD_RELOC_M68HC11_HI8
Motorola 68HC11 reloc.
This is the 8 bit high part of an absolute address.
@end deffn
@deffn {} BFD_RELOC_M68HC11_LO8
Motorola 68HC11 reloc.
This is the 8 bit low part of an absolute address.
@end deffn
@deffn {} BFD_RELOC_M68HC11_3B
Motorola 68HC11 reloc.
This is the 3 bit of a value.
@end deffn
@deffn {} BFD_RELOC_M68HC11_RL_JUMP
Motorola 68HC11 reloc.
This reloc marks the beginning of a jump/call instruction.
It is used for linker relaxation to correctly identify beginning
of instruction and change some branchs to use PC-relative
addressing mode.
@end deffn
@deffn {} BFD_RELOC_M68HC11_RL_GROUP
Motorola 68HC11 reloc.
This reloc marks a group of several instructions that gcc generates
and for which the linker relaxation pass can modify and/or remove
some of them.
@end deffn
@deffn {} BFD_RELOC_M68HC11_LO16
Motorola 68HC11 reloc.
This is the 16-bit lower part of an address.  It is used for 'call'
instruction to specify the symbol address without any special
transformation (due to memory bank window).
@end deffn
@deffn {} BFD_RELOC_M68HC11_PAGE
Motorola 68HC11 reloc.
This is a 8-bit reloc that specifies the page number of an address.
It is used by 'call' instruction to specify the page number of
the symbol.
@end deffn
@deffn {} BFD_RELOC_M68HC11_24
Motorola 68HC11 reloc.
This is a 24-bit reloc that represents the address with a 16-bit
value and a 8-bit page number.  The symbol address is transformed
to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
@end deffn
@deffn {} BFD_RELOC_CRIS_BDISP8
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_5
@deffnx {} BFD_RELOC_CRIS_SIGNED_6
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_6
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_4
These relocs are only used within the CRIS assembler.  They are not
(at present) written to any object files.
@end deffn
@deffn {} BFD_RELOC_CRIS_COPY
@deffnx {} BFD_RELOC_CRIS_GLOB_DAT
@deffnx {} BFD_RELOC_CRIS_JUMP_SLOT
@deffnx {} BFD_RELOC_CRIS_RELATIVE
Relocs used in ELF shared libraries for CRIS.
@end deffn
@deffn {} BFD_RELOC_CRIS_32_GOT
32-bit offset to symbol-entry within GOT.
@end deffn
@deffn {} BFD_RELOC_CRIS_16_GOT
16-bit offset to symbol-entry within GOT.
@end deffn
@deffn {} BFD_RELOC_CRIS_32_GOTPLT
32-bit offset to symbol-entry within GOT, with PLT handling.
@end deffn
@deffn {} BFD_RELOC_CRIS_16_GOTPLT
16-bit offset to symbol-entry within GOT, with PLT handling.
@end deffn
@deffn {} BFD_RELOC_CRIS_32_GOTREL
32-bit offset to symbol, relative to GOT.
@end deffn
@deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL
32-bit offset to symbol with PLT entry, relative to GOT.
@end deffn
@deffn {} BFD_RELOC_CRIS_32_PLT_PCREL
32-bit offset to symbol with PLT entry, relative to this relocation.
@end deffn
@deffn {} BFD_RELOC_860_COPY
@deffnx {} BFD_RELOC_860_GLOB_DAT
@deffnx {} BFD_RELOC_860_JUMP_SLOT
@deffnx {} BFD_RELOC_860_RELATIVE
@deffnx {} BFD_RELOC_860_PC26
@deffnx {} BFD_RELOC_860_PLT26
@deffnx {} BFD_RELOC_860_PC16
@deffnx {} BFD_RELOC_860_LOW0
@deffnx {} BFD_RELOC_860_SPLIT0
@deffnx {} BFD_RELOC_860_LOW1
@deffnx {} BFD_RELOC_860_SPLIT1
@deffnx {} BFD_RELOC_860_LOW2
@deffnx {} BFD_RELOC_860_SPLIT2
@deffnx {} BFD_RELOC_860_LOW3
@deffnx {} BFD_RELOC_860_LOGOT0
@deffnx {} BFD_RELOC_860_SPGOT0
@deffnx {} BFD_RELOC_860_LOGOT1
@deffnx {} BFD_RELOC_860_SPGOT1
@deffnx {} BFD_RELOC_860_LOGOTOFF0
@deffnx {} BFD_RELOC_860_SPGOTOFF0
@deffnx {} BFD_RELOC_860_LOGOTOFF1
@deffnx {} BFD_RELOC_860_SPGOTOFF1
@deffnx {} BFD_RELOC_860_LOGOTOFF2
@deffnx {} BFD_RELOC_860_LOGOTOFF3
@deffnx {} BFD_RELOC_860_LOPC
@deffnx {} BFD_RELOC_860_HIGHADJ
@deffnx {} BFD_RELOC_860_HAGOT
@deffnx {} BFD_RELOC_860_HAGOTOFF
@deffnx {} BFD_RELOC_860_HAPC
@deffnx {} BFD_RELOC_860_HIGH
@deffnx {} BFD_RELOC_860_HIGOT
@deffnx {} BFD_RELOC_860_HIGOTOFF
Intel i860 Relocations.
@end deffn
@deffn {} BFD_RELOC_OPENRISC_ABS_26
@deffnx {} BFD_RELOC_OPENRISC_REL_26
OpenRISC Relocations.
@end deffn
@deffn {} BFD_RELOC_H8_DIR16A8
@deffnx {} BFD_RELOC_H8_DIR16R8
@deffnx {} BFD_RELOC_H8_DIR24A8
@deffnx {} BFD_RELOC_H8_DIR24R8
@deffnx {} BFD_RELOC_H8_DIR32A16
H8 elf Relocations.
@end deffn
@deffn {} BFD_RELOC_XSTORMY16_REL_12
@deffnx {} BFD_RELOC_XSTORMY16_12
@deffnx {} BFD_RELOC_XSTORMY16_24
@deffnx {} BFD_RELOC_XSTORMY16_FPTR16
Sony Xstormy16 Relocations.
@end deffn
@deffn {} BFD_RELOC_VAX_GLOB_DAT
@deffnx {} BFD_RELOC_VAX_JMP_SLOT
@deffnx {} BFD_RELOC_VAX_RELATIVE
Relocations used by VAX ELF.
@end deffn
@deffn {} BFD_RELOC_MSP430_10_PCREL
@deffnx {} BFD_RELOC_MSP430_16_PCREL
@deffnx {} BFD_RELOC_MSP430_16
@deffnx {} BFD_RELOC_MSP430_16_PCREL_BYTE
@deffnx {} BFD_RELOC_MSP430_16_BYTE
msp430 specific relocation codes
@end deffn
@deffn {} BFD_RELOC_IQ2000_OFFSET_16
@deffnx {} BFD_RELOC_IQ2000_OFFSET_21
@deffnx {} BFD_RELOC_IQ2000_UHI16
IQ2000 Relocations.
@end deffn
@deffn {} BFD_RELOC_XTENSA_RTLD
Special Xtensa relocation used only by PLT entries in ELF shared
objects to indicate that the runtime linker should set the value
to one of its own internal functions or data structures.
@end deffn
@deffn {} BFD_RELOC_XTENSA_GLOB_DAT
@deffnx {} BFD_RELOC_XTENSA_JMP_SLOT
@deffnx {} BFD_RELOC_XTENSA_RELATIVE
Xtensa relocations for ELF shared objects.
@end deffn
@deffn {} BFD_RELOC_XTENSA_PLT
Xtensa relocation used in ELF object files for symbols that may require
PLT entries.  Otherwise, this is just a generic 32-bit relocation.
@end deffn
@deffn {} BFD_RELOC_XTENSA_OP0
@deffnx {} BFD_RELOC_XTENSA_OP1
@deffnx {} BFD_RELOC_XTENSA_OP2
Generic Xtensa relocations.  Only the operand number is encoded
in the relocation.  The details are determined by extracting the
instruction opcode.
@end deffn
@deffn {} BFD_RELOC_XTENSA_ASM_EXPAND
Xtensa relocation to mark that the assembler expanded the 
instructions from an original target.  The expansion size is
encoded in the reloc size.
@end deffn
@deffn {} BFD_RELOC_XTENSA_ASM_SIMPLIFY
Xtensa relocation to mark that the linker should simplify 
assembler-expanded instructions.  This is commonly used 
internally by the linker after analysis of a 
BFD_RELOC_XTENSA_ASM_EXPAND.
@end deffn

@example

typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
@end example
@findex bfd_reloc_type_lookup
@subsubsection @code{bfd_reloc_type_lookup}
@strong{Synopsis}
@example
reloc_howto_type *
bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code);
@end example
@strong{Description}@*
Retu