reloc.texi

gdb-6.0 linux 下的调试工具

High 16 bits of 32-bit value but the low 16 bits will be sign
extended and added to form the final result.  If the low 16
bits form a negative number, we need to add one to the high value
to compensate for the borrow when the low bits are added.
@end deffn
@deffn {} BFD_RELOC_LO16
Low 16 bits.
@end deffn
@deffn {} BFD_RELOC_PCREL_HI16_S
Like BFD_RELOC_HI16_S, but PC relative.
@end deffn
@deffn {} BFD_RELOC_PCREL_LO16
Like BFD_RELOC_LO16, but PC relative.
@end deffn
@deffn {} BFD_RELOC_MIPS_LITERAL
Relocation against a MIPS literal section.
@end deffn
@deffn {} BFD_RELOC_MIPS_GOT16
@deffnx {} BFD_RELOC_MIPS_CALL16
@deffnx {} BFD_RELOC_MIPS_GOT_HI16
@deffnx {} BFD_RELOC_MIPS_GOT_LO16
@deffnx {} BFD_RELOC_MIPS_CALL_HI16
@deffnx {} BFD_RELOC_MIPS_CALL_LO16
@deffnx {} BFD_RELOC_MIPS_SUB
@deffnx {} BFD_RELOC_MIPS_GOT_PAGE
@deffnx {} BFD_RELOC_MIPS_GOT_OFST
@deffnx {} BFD_RELOC_MIPS_GOT_DISP
@deffnx {} BFD_RELOC_MIPS_SHIFT5
@deffnx {} BFD_RELOC_MIPS_SHIFT6
@deffnx {} BFD_RELOC_MIPS_INSERT_A
@deffnx {} BFD_RELOC_MIPS_INSERT_B
@deffnx {} BFD_RELOC_MIPS_DELETE
@deffnx {} BFD_RELOC_MIPS_HIGHEST
@deffnx {} BFD_RELOC_MIPS_HIGHER
@deffnx {} BFD_RELOC_MIPS_SCN_DISP
@deffnx {} BFD_RELOC_MIPS_REL16
@deffnx {} BFD_RELOC_MIPS_RELGOT
@deffnx {} BFD_RELOC_MIPS_JALR
@deffn {} BFD_RELOC_FRV_LABEL16
@deffnx {} BFD_RELOC_FRV_LABEL24
@deffnx {} BFD_RELOC_FRV_LO16
@deffnx {} BFD_RELOC_FRV_HI16
@deffnx {} BFD_RELOC_FRV_GPREL12
@deffnx {} BFD_RELOC_FRV_GPRELU12
@deffnx {} BFD_RELOC_FRV_GPREL32
@deffnx {} BFD_RELOC_FRV_GPRELHI
@deffnx {} BFD_RELOC_FRV_GPRELLO
Fujitsu Frv Relocations.
@end deffn
MIPS ELF relocations.
@end deffn
@deffn {} BFD_RELOC_386_GOT32
@deffnx {} BFD_RELOC_386_PLT32
@deffnx {} BFD_RELOC_386_COPY
@deffnx {} BFD_RELOC_386_GLOB_DAT
@deffnx {} BFD_RELOC_386_JUMP_SLOT
@deffnx {} BFD_RELOC_386_RELATIVE
@deffnx {} BFD_RELOC_386_GOTOFF
@deffnx {} BFD_RELOC_386_GOTPC
@deffnx {} BFD_RELOC_386_TLS_TPOFF
@deffnx {} BFD_RELOC_386_TLS_IE
@deffnx {} BFD_RELOC_386_TLS_GOTIE
@deffnx {} BFD_RELOC_386_TLS_LE
@deffnx {} BFD_RELOC_386_TLS_GD
@deffnx {} BFD_RELOC_386_TLS_LDM
@deffnx {} BFD_RELOC_386_TLS_LDO_32
@deffnx {} BFD_RELOC_386_TLS_IE_32
@deffnx {} BFD_RELOC_386_TLS_LE_32
@deffnx {} BFD_RELOC_386_TLS_DTPMOD32
@deffnx {} BFD_RELOC_386_TLS_DTPOFF32
@deffnx {} BFD_RELOC_386_TLS_TPOFF32
i386/elf relocations
@end deffn
@deffn {} BFD_RELOC_X86_64_GOT32
@deffnx {} BFD_RELOC_X86_64_PLT32
@deffnx {} BFD_RELOC_X86_64_COPY
@deffnx {} BFD_RELOC_X86_64_GLOB_DAT
@deffnx {} BFD_RELOC_X86_64_JUMP_SLOT
@deffnx {} BFD_RELOC_X86_64_RELATIVE
@deffnx {} BFD_RELOC_X86_64_GOTPCREL
@deffnx {} BFD_RELOC_X86_64_32S
@deffnx {} BFD_RELOC_X86_64_DTPMOD64
@deffnx {} BFD_RELOC_X86_64_DTPOFF64
@deffnx {} BFD_RELOC_X86_64_TPOFF64
@deffnx {} BFD_RELOC_X86_64_TLSGD
@deffnx {} BFD_RELOC_X86_64_TLSLD
@deffnx {} BFD_RELOC_X86_64_DTPOFF32
@deffnx {} BFD_RELOC_X86_64_GOTTPOFF
@deffnx {} BFD_RELOC_X86_64_TPOFF32
x86-64/elf relocations
@end deffn
@deffn {} BFD_RELOC_NS32K_IMM_8
@deffnx {} BFD_RELOC_NS32K_IMM_16
@deffnx {} BFD_RELOC_NS32K_IMM_32
@deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL
@deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL
@deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL
@deffnx {} BFD_RELOC_NS32K_DISP_8
@deffnx {} BFD_RELOC_NS32K_DISP_16
@deffnx {} BFD_RELOC_NS32K_DISP_32
@deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL
@deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL
@deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL
ns32k relocations
@end deffn
@deffn {} BFD_RELOC_PDP11_DISP_8_PCREL
@deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL
PDP11 relocations
@end deffn
@deffn {} BFD_RELOC_PJ_CODE_HI16
@deffnx {} BFD_RELOC_PJ_CODE_LO16
@deffnx {} BFD_RELOC_PJ_CODE_DIR16
@deffnx {} BFD_RELOC_PJ_CODE_DIR32
@deffnx {} BFD_RELOC_PJ_CODE_REL16
@deffnx {} BFD_RELOC_PJ_CODE_REL32
Picojava relocs.  Not all of these appear in object files.
@end deffn
@deffn {} BFD_RELOC_PPC_B26
@deffnx {} BFD_RELOC_PPC_BA26
@deffnx {} BFD_RELOC_PPC_TOC16
@deffnx {} BFD_RELOC_PPC_B16
@deffnx {} BFD_RELOC_PPC_B16_BRTAKEN
@deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN
@deffnx {} BFD_RELOC_PPC_BA16
@deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN
@deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN
@deffnx {} BFD_RELOC_PPC_COPY
@deffnx {} BFD_RELOC_PPC_GLOB_DAT
@deffnx {} BFD_RELOC_PPC_JMP_SLOT
@deffnx {} BFD_RELOC_PPC_RELATIVE
@deffnx {} BFD_RELOC_PPC_LOCAL24PC
@deffnx {} BFD_RELOC_PPC_EMB_NADDR32
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA
@deffnx {} BFD_RELOC_PPC_EMB_SDAI16
@deffnx {} BFD_RELOC_PPC_EMB_SDA2I16
@deffnx {} BFD_RELOC_PPC_EMB_SDA2REL
@deffnx {} BFD_RELOC_PPC_EMB_SDA21
@deffnx {} BFD_RELOC_PPC_EMB_MRKREF
@deffnx {} BFD_RELOC_PPC_EMB_RELSEC16
@deffnx {} BFD_RELOC_PPC_EMB_RELST_LO
@deffnx {} BFD_RELOC_PPC_EMB_RELST_HI
@deffnx {} BFD_RELOC_PPC_EMB_RELST_HA
@deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD
@deffnx {} BFD_RELOC_PPC_EMB_RELSDA
@deffnx {} BFD_RELOC_PPC64_HIGHER
@deffnx {} BFD_RELOC_PPC64_HIGHER_S
@deffnx {} BFD_RELOC_PPC64_HIGHEST
@deffnx {} BFD_RELOC_PPC64_HIGHEST_S
@deffnx {} BFD_RELOC_PPC64_TOC16_LO
@deffnx {} BFD_RELOC_PPC64_TOC16_HI
@deffnx {} BFD_RELOC_PPC64_TOC16_HA
@deffnx {} BFD_RELOC_PPC64_TOC
@deffnx {} BFD_RELOC_PPC64_PLTGOT16
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA
@deffnx {} BFD_RELOC_PPC64_ADDR16_DS
@deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS
@deffnx {} BFD_RELOC_PPC64_GOT16_DS
@deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS
@deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS
@deffnx {} BFD_RELOC_PPC64_SECTOFF_DS
@deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS
@deffnx {} BFD_RELOC_PPC64_TOC16_DS
@deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS
Power(rs6000) and PowerPC relocations.
@end deffn
@deffn {} BFD_RELOC_PPC_TLS
@deffnx {} BFD_RELOC_PPC_DTPMOD
@deffnx {} BFD_RELOC_PPC_TPREL16
@deffnx {} BFD_RELOC_PPC_TPREL16_LO
@deffnx {} BFD_RELOC_PPC_TPREL16_HI
@deffnx {} BFD_RELOC_PPC_TPREL16_HA
@deffnx {} BFD_RELOC_PPC_TPREL
@deffnx {} BFD_RELOC_PPC_DTPREL16
@deffnx {} BFD_RELOC_PPC_DTPREL16_LO
@deffnx {} BFD_RELOC_PPC_DTPREL16_HI
@deffnx {} BFD_RELOC_PPC_DTPREL16_HA
@deffnx {} BFD_RELOC_PPC_DTPREL
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_LO
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HI
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HA
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_LO
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HI
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HA
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_LO
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HI
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HA
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_LO
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HI
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HA
@deffnx {} BFD_RELOC_PPC64_TPREL16_DS
@deffnx {} BFD_RELOC_PPC64_TPREL16_LO_DS
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHER
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHERA
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHEST
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHESTA
@deffnx {} BFD_RELOC_PPC64_DTPREL16_DS
@deffnx {} BFD_RELOC_PPC64_DTPREL16_LO_DS
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHER
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHERA
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHEST
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHESTA
PowerPC and PowerPC64 thread-local storage relocations.
@end deffn
@deffn {} BFD_RELOC_I370_D12
IBM 370/390 relocations
@end deffn
@deffn {} BFD_RELOC_CTOR
The type of reloc used to build a contructor table - at the moment
probably a 32 bit wide absolute relocation, but the target can choose.
It generally does map to one of the other relocation types.
@end deffn
@deffn {} BFD_RELOC_ARM_PCREL_BRANCH
ARM 26 bit pc-relative branch.  The lowest two bits must be zero and are
not stored in the instruction.
@end deffn
@deffn {} BFD_RELOC_ARM_PCREL_BLX
ARM 26 bit pc-relative branch.  The lowest bit must be zero and is
not stored in the instruction.  The 2nd lowest bit comes from a 1 bit
field in the instruction.
@end deffn
@deffn {} BFD_RELOC_THUMB_PCREL_BLX
Thumb 22 bit pc-relative branch.  The lowest bit must be zero and is
not stored in the instruction.  The 2nd lowest bit comes from a 1 bit
field in the instruction.
@end deffn
@deffn {} BFD_RELOC_ARM_IMMEDIATE
@deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE
@deffnx {} BFD_RELOC_ARM_OFFSET_IMM
@deffnx {} BFD_RELOC_ARM_SHIFT_IMM
@deffnx {} BFD_RELOC_ARM_SWI
@deffnx {} BFD_RELOC_ARM_MULTI
@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM
@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM_S2
@deffnx {} BFD_RELOC_ARM_ADR_IMM
@deffnx {} BFD_RELOC_ARM_LDR_IMM
@deffnx {} BFD_RELOC_ARM_LITERAL
@deffnx {} BFD_RELOC_ARM_IN_POOL
@deffnx {} BFD_RELOC_ARM_OFFSET_IMM8
@deffnx {} BFD_RELOC_ARM_HWLITERAL
@deffnx {} BFD_RELOC_ARM_THUMB_ADD
@deffnx {} BFD_RELOC_ARM_THUMB_IMM
@deffnx {} BFD_RELOC_ARM_THUMB_SHIFT
@deffnx {} BFD_RELOC_ARM_THUMB_OFFSET
@deffnx {} BFD_RELOC_ARM_GOT12
@deffnx {} BFD_RELOC_ARM_GOT32
@deffnx {} BFD_RELOC_ARM_JUMP_SLOT
@deffnx {} BFD_RELOC_ARM_COPY
@deffnx {} BFD_RELOC_ARM_GLOB_DAT
@deffnx {} BFD_RELOC_ARM_PLT32
@deffnx {} BFD_RELOC_ARM_RELATIVE
@deffnx {} BFD_RELOC_ARM_GOTOFF
@deffnx {} BFD_RELOC_ARM_GOTPC
These relocs are only used within the ARM assembler.  They are not
(at present) written to any object files.
@end deffn
@deffn {} BFD_RELOC_SH_PCDISP8BY2
@deffnx {} BFD_RELOC_SH_PCDISP12BY2
@deffnx {} BFD_RELOC_SH_IMM4
@deffnx {} BFD_RELOC_SH_IMM4BY2
@deffnx {} BFD_RELOC_SH_IMM4BY4
@deffnx {} BFD_RELOC_SH_IMM8
@deffnx {} BFD_RELOC_SH_IMM8BY2
@deffnx {} BFD_RELOC_SH_IMM8BY4
@deffnx {} BFD_RELOC_SH_PCRELIMM8BY2
@deffnx {} BFD_RELOC_SH_PCRELIMM8BY4
@deffnx {} BFD_RELOC_SH_SWITCH16
@deffnx {} BFD_RELOC_SH_SWITCH32
@deffnx {} BFD_RELOC_SH_USES
@deffnx {} BFD_RELOC_SH_COUNT
@deffnx {} BFD_RELOC_SH_ALIGN
@deffnx {} BFD_RELOC_SH_CODE
@deffnx {} BFD_RELOC_SH_DATA
@deffnx {} BFD_RELOC_SH_LABEL
@deffnx {} BFD_RELOC_SH_LOOP_START
@deffnx {} BFD_RELOC_SH_LOOP_END
@deffnx {} BFD_RELOC_SH_COPY
@deffnx {} BFD_RELOC_SH_GLOB_DAT
@deffnx {} BFD_RELOC_SH_JMP_SLOT
@deffnx {} BFD_RELOC_SH_RELATIVE
@deffnx {} BFD_RELOC_SH_GOTPC
@deffnx {} BFD_RELOC_SH_GOT_LOW16
@deffnx {} BFD_RELOC_SH_GOT_MEDLOW16
@deffnx {} BFD_RELOC_SH_GOT_MEDHI16
@deffnx {} BFD_RELOC_SH_GOT_HI16
@deffnx {} BFD_RELOC_SH_GOTPLT_LOW16
@deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16
@deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16
@deffnx {} BFD_RELOC_SH_GOTPLT_HI16
@deffnx {} BFD_RELOC_SH_PLT_LOW16
@deffnx {} BFD_RELOC_SH_PLT_MEDLOW16
@deffnx {} BFD_RELOC_SH_PLT_MEDHI16
@deffnx {} BFD_RELOC_SH_PLT_HI16
@deffnx {} BFD_RELOC_SH_GOTOFF_LOW16
@deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16
@deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16
@deffnx {} BFD_RELOC_SH_GOTOFF_HI16
@deffnx {} BFD_RELOC_SH_GOTPC_LOW16
@deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16
@deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16
@deffnx {} BFD_RELOC_SH_GOTPC_HI16
@deffnx {} BFD_RELOC_SH_COPY64
@deffnx {} BFD_RELOC_SH_GLOB_DAT64
@deffnx {} BFD_RELOC_SH_JMP_SLOT64
@deffnx {} BFD_RELOC_SH_RELATIVE64
@deffnx {} BFD_RELOC_SH_GOT10BY4
@deffnx {} BFD_RELOC_SH_GOT10BY8
@deffnx {} BFD_RELOC_SH_GOTPLT10BY4
@deffnx {} BFD_RELOC_SH_GOTPLT10BY8
@deffnx {} BFD_RELOC_SH_GOTPLT32
@deffnx {} BFD_RELOC_SH_SHMEDIA_CODE
@deffnx {} BFD_RELOC_SH_IMMU5
@deffnx {} BFD_RELOC_SH_IMMS6
@deffnx {} BFD_RELOC_SH_IMMS6BY32
@deffnx {} BFD_RELOC_SH_IMMU6
@deffnx {} BFD_RELOC_SH_IMMS10
@deffnx {} BFD_RELOC_SH_IMMS10BY2
@deffnx {} BFD_RELOC_SH_IMMS10BY4
@deffnx {} BFD_RELOC_SH_IMMS10BY8
@deffnx {} BFD_RELOC_SH_IMMS16
@deffnx {} BFD_RELOC_SH_IMMU16
@deffnx {} BFD_RELOC_SH_IMM_LOW16
@deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL
@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16
@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL
@deffnx {} BFD_RELOC_SH_IMM_MEDHI16
@deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL
@deffnx {} BFD_RELOC_SH_IMM_HI16
@deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL
@deffnx {} BFD_RELOC_SH_PT_16
@deffnx {} BFD_RELOC_SH_TLS_GD_32
@deffnx {} BFD_RELOC_SH_TLS_LD_32
@deffnx {} BFD_RELOC_SH_TLS_LDO_32
@deffnx {} BFD_RELOC_SH_TLS_IE_32
@deffnx {} BFD_RELOC_SH_TLS_LE_32
@deffnx {} BFD_RELOC_SH_TLS_DTPMOD32
@deffnx {} BFD_RELOC_SH_TLS_DTPOFF32
@deffnx {} BFD_RELOC_SH_TLS_TPOFF32
Renesas / SuperH SH relocs.  Not all of these appear in object files.
@end deffn
@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH9
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23
Thumb 23-, 12- and 9-bit pc-relative branches.  The lowest bit must
be zero and is not stored in the instruction.
@end deffn
@deffn {} BFD_RELOC_ARC_B22_PCREL
ARC Cores relocs.
ARC 22 bit pc-relative branch.  The lowest two bits must be zero and are
not stored in the instruction.  The high 20 bits are installed in bits 26
through 7 of the instruction.
@end deffn
@deffn {} BFD_RELOC_ARC_B26
ARC 26 bit absolute branch.  The lowest two bits must be zero and are not
stored in the instruction.  The high 24 bits are installed in bits 23
through 0.
@end deffn
@deffn {} BFD_RELOC_D10V_10_PCREL_R
Mitsubishi D10V relocs.
This is a 10-bit reloc with the right 2 bits
assumed to be 0.
@end deffn
@deffn {} BFD_RELOC_D10V_10_PCREL_L
Mitsubishi D10V relocs.
This is a 10-bit reloc with the right 2 bits
assumed to be 0.  This is the same as the previous reloc
except it is in the left container, i.e.,
shifted left 15 bits.
@end deffn
@deffn {} BFD_RELOC_D10V_18
This is an 18-bit reloc with the right 2 bits
assumed to be 0.
@end deffn
@deffn {} BFD_RELOC_D10V_18_PCREL
This is an 18-bit reloc with the right 2 bits
assumed to be 0.