h8300.md

gcc-2.95.3 Linux下最常用的C编译器

(define_expand "extendhisi2_h8300"
  [(set (reg:HI 1) (match_operand:HI 1 "general_operand" ""))
   (set (reg:SI 0) (sign_extend:SI (reg:HI 1)))
   (set (match_operand:SI 0 "general_operand" "" ) (reg:SI 0))]
  "TARGET_H8300"
  "")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
  "TARGET_H8300"
  "@
  bld	#7,%x0\;subx	%y0,%y0\;subx	%z0,%z0
  mov.w	%T1,%f0\;bld	#7,%x0\;subx	%y0,%y0\;subx	%z0,%z0"
  [(set_attr "length" "6,8")
   (set_attr "cc" "clobber,clobber")])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
  "TARGET_H8300H || TARGET_H8300S"
  "exts.l	%S0"
  [(set_attr "length" "2")
   (set_attr "cc" "set_znv")])

;; ----------------------------------------------------------------------
;; SHIFTS
;; ----------------------------------------------------------------------
;;
;; We make some attempt to provide real efficient shifting.  One example is
;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
;; reg and moving 0 into the former reg.
;;
;; We also try to achieve this in a uniform way.  IE: We don't try to achieve
;; this in both rtl and at insn emit time.  Ideally, we'd use rtl as that would
;; give the optimizer more cracks at the code.  However, we wish to do things
;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
;; There is rtl to handle this (rotate + and), but the h8/300 doesn't handle
;; 16 bit rotates.  Also, if we emit complicated rtl, combine may not be able
;; to detect cases it can optimize.
;;
;; For these and other fuzzy reasons, I've decided to go the less pretty but
;; easier "do it at insn emit time" route.

;; QI BIT SHIFTS

(define_expand "ashlqi3"
  [(set (match_operand:QI 0 "register_operand" "")
	(ashift:QI (match_operand:QI 1 "register_operand" "")
		   (match_operand:QI 2 "nonmemory_operand" "")))]
  ""
  "if (expand_a_shift (QImode, ASHIFT, operands)) DONE;else FAIL;")

(define_expand "ashrqi3"
  [(set (match_operand:QI 0 "register_operand" "")
	(ashiftrt:QI (match_operand:QI 1 "register_operand" "")
		     (match_operand:QI 2 "nonmemory_operand" "")))]
  ""
  "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE;else FAIL;")

(define_expand "lshrqi3"
  [(set (match_operand:QI 0 "register_operand" "")
	(lshiftrt:QI (match_operand:QI 1 "register_operand" "")
		     (match_operand:QI 2 "nonmemory_operand" "")))]
  ""
  "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE;else FAIL;")

(define_insn ""
  [(set (match_operand:QI 0 "register_operand" "=r,r")
	(match_operator:QI 3 "nshift_operator" 
			[ (match_operand:QI 1 "register_operand" "0,0")
			  (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
   (clobber (match_scratch:QI 4 "=X,&r"))]
  ""
  "* return emit_a_shift (insn, operands);"
  [(set_attr "length" "20")
   (set_attr "cc" "clobber")])

;; HI BIT SHIFTS

(define_expand "ashlhi3"
  [(set (match_operand:HI 0 "register_operand" "")
	(ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
		   (match_operand:QI 2 "nonmemory_operand" "")))]
  ""
  "if (expand_a_shift (HImode, ASHIFT, operands)) DONE;else FAIL;")

(define_expand "lshrhi3"
  [(set (match_operand:HI 0 "register_operand" "")
	(lshiftrt:HI (match_operand:HI 1 "general_operand" "")
		     (match_operand:QI 2 "nonmemory_operand" "")))]
  ""
  "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE;else FAIL;")

(define_expand "ashrhi3"
  [(set (match_operand:HI 0 "register_operand" "")
	(ashiftrt:HI (match_operand:HI 1 "register_operand" "")
		     (match_operand:QI 2 "nonmemory_operand" "")))]
  ""
  "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE;else FAIL;")

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=r,r")
	(match_operator:HI 3 "nshift_operator" 
			[ (match_operand:HI 1 "register_operand" "0,0")
			  (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
   (clobber (match_scratch:QI 4 "=X,&r"))]
  ""
  "* return emit_a_shift (insn, operands);"
  [(set_attr "length" "20")
   (set_attr "cc" "clobber")])

;;  SI BIT SHIFTS

(define_expand "ashlsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(ashift:SI
	 (match_operand:SI 1 "general_operand" "")
	 (match_operand:QI 2 "nonmemory_operand" "")))]
  ""
  "if (expand_a_shift (SImode, ASHIFT, operands)) DONE;else FAIL;")

(define_expand "lshrsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(lshiftrt:SI
	 (match_operand:SI 1 "general_operand" "")
	 (match_operand:QI 2 "nonmemory_operand" "")))]
  ""
  "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE;else FAIL;")

(define_expand "ashrsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(ashiftrt:SI
	 (match_operand:SI 1 "general_operand" "")
	 (match_operand:QI 2 "nonmemory_operand" "")))]
  ""
  "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE;else FAIL;")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(match_operator:SI 3 "nshift_operator" 
			[ (match_operand:SI 1 "register_operand" "0,0")
			  (match_operand:QI 2 "nonmemory_operand" "K,rn")]))
   (clobber (match_scratch:QI 4 "=X,&r"))]
  ""
  "* return emit_a_shift (insn, operands);"
  [(set_attr "length" "20")
   (set_attr "cc" "clobber")])

;; -----------------------------------------------------------------
;; BIT FIELDS
;; -----------------------------------------------------------------
;; The H8/300 has given 1/8th of its opcode space to bitfield
;; instructions so let's use them as well as we can.

;; You'll never believe all these patterns perform one basic action --
;; load a bit from the source, optionally invert the bit, then store it
;; in the destination (which is known to be zero)..  
;;
;; Combine obviously need some work to better identify this situation and
;; canonicalize the form better.

;; 
;; Normal loads with a 16bit destination.
;; 
;; Yes, both cases are needed.
;;
(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=&r")
	(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
			 (const_int 1)
			 (match_operand:HI 2 "immediate_operand" "n")))]
  ""
  "sub.w	%0,%0\;bld	%Z2,%Y1\;bst	#0,%X0"
  [(set_attr "cc" "clobber")
   (set_attr "length" "6")])

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=&r")
	(subreg:HI (zero_extract:SI
		     (match_operand:HI 1 "register_operand" "r")
		     (const_int 1)
		     (match_operand:HI 2 "immediate_operand" "n")) 1))]
  ""
  "sub.w	%0,%0\;bld	%Z2,%Y1\;bst	#0,%X0"
  [(set_attr "cc" "clobber")
   (set_attr "length" "6")])

;; 
;; Inverted loads with a 16bit destination.
;; 
;; Yes, all four cases are needed.
;;

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=&r")
	(zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
				 (match_operand:HI 3 "p_operand" "P"))
			 (const_int 1)
			 (match_operand:HI 2 "const_int_operand" "n")))]
  "(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
  "sub.w	%0,%0\;bild	%Z2,%Y1\;bst	#0,%X0"
  [(set_attr "cc" "clobber")
   (set_attr "length" "8")])

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=&r")
	(and:HI (not:HI 
		  (lshiftrt:HI
		    (match_operand:HI 1 "bit_operand" "Ur")
		    (match_operand:HI 2 "const_int_operand" "n")))
		(const_int 1)))]
  ""
  "sub.w	%0,%0\;bild	%Z2,%Y1\;bst	#0,%X0"
  [(set_attr "cc" "clobber")
   (set_attr "length" "8")])

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=&r")
	(and:HI (not:HI 
		  (subreg:HI 
		    (lshiftrt:SI
		      (match_operand:SI 1 "register_operand" "Ur")
		      (match_operand:SI 2 "const_int_operand" "n")) 1))
		(const_int 1)))]
  "INTVAL (operands[2]) < 16"
  "sub.w	%0,%0\;bild	%Z2,%Y1\;bst	#0,%X0"
  [(set_attr "cc" "clobber")
   (set_attr "length" "8")])

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=&r")
	(and:HI (not:HI 
		  (subreg:HI 
		    (lshiftrt:SI
		      (match_operand:SI 1 "bit_operand" "Ur")
		      (match_operand:SI 2 "const_int_operand" "n")) 0))
		(const_int 1)))]
  "(TARGET_H8300H || TARGET_H8300S)
   && INTVAL (operands[2]) < 16"
  "sub.w	%0,%0\;bild	%Z2,%Y1\;bst	#0,%X0"
  [(set_attr "cc" "clobber")
   (set_attr "length" "8")])

;; 
;; Normal loads with a 32bit destination.
;; 
;; Yes, all three cases are needed.
;;
(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=&r")
	(zero_extract:SI (match_operand:HI 1 "register_operand" "r")
			 (const_int 1)
			 (match_operand:HI 2 "const_int_operand" "n")))]
  ""
  "* return output_simode_bld (0, 0, operands);"
  [(set_attr "cc" "clobber")
   (set (attr "length")
	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
			  (const_int 0))
		      (const_int 10)
		      (const_int 8)))])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=&r")
	(and:SI (zero_extend:SI 
		   (lshiftrt:QI
		     (match_operand:QI 1 "bit_operand" "Ur")
		     (match_operand:QI 2 "const_int_operand" "n")))
		(const_int 1)))]
  ""
  "* return output_simode_bld (0, 0, operands);"
  [(set_attr "cc" "clobber")
   (set (attr "length")
	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
			  (const_int 0))
		      (const_int 10)
		      (const_int 8)))])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=&r")
	(and:SI (zero_extend:SI 
		   (lshiftrt:HI
		      (match_operand:HI 1 "bit_operand" "Ur")
		      (match_operand:HI 2 "const_int_operand" "n")))
		(const_int 1)))]
  ""
  "* return output_simode_bld (0, 0, operands);"
  [(set_attr "cc" "clobber")
   (set (attr "length")
	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
			  (const_int 0))
		      (const_int 10)
		      (const_int 8)))])

;; 
;; Inverted loads with a 32bit destination.
;; 
;; Yes, all seven cases are needed.
;;
(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=&r")
	(and:SI (not:SI
		  (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))
		(match_operand:SI 2 "p_operand" "P")))]
  ""
  "* return output_simode_bld (1, 1, operands);"
  [(set_attr "cc" "clobber")
   (set (attr "length")
	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
			  (const_int 0))
		      (const_int 10)
		      (const_int 8)))])
(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=&r")
	(and:SI (not:SI
		  (zero_extend:SI
		    (lshiftrt:HI (match_operand:HI 1 "bit_operand" "Ur")
				 (match_operand:HI 2 "const_int_operand" "n"))))
		(const_int 1)))]
  ""
  "* return output_simode_bld (1, 0, operands);"
  [(set_attr "cc" "clobber")
   (set (attr "length")
	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
			  (const_int 0))
		      (const_int 10)
		      (const_int 8)))])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=&r")
	(and:SI (not:SI
		  (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))
		(match_operand:SI 2 "p_operand" "P")))]
  ""
  "* return output_simode_bld (1, 1, operands);"
  [(set_attr "cc" "clobber")
   (set (attr "length")
	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
			  (const_int 0))
		      (const_int 10)
		      (const_int 8)))])
(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=&r")
	(and:SI (not:SI
		  (zero_extend:SI
		    (lshiftrt:QI (match_operand:QI 1 "bit_operand" "Ur")
				 (match_operand:QI 2 "const_int_operand" "n"))))
		(const_int 1)))]
  ""
  "* return output_simode_bld (1, 0, operands);"
  [(set_attr "cc" "clobber")
   (set (attr "length")
	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
			  (const_int 0))
		      (const_int 10)
		      (const_int 8)))])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=&r")
	(and:SI (not:SI
		  (subreg:SI 
		     (lshiftrt:HI
			(match_operand:HI 1 "bit_operand" "Ur")
			(match_operand:HI 2 "const_int_operand" "n")) 0))
		(const_int 1)))]
  "1"
  "* return output_simode_bld (1, 0, operands);"
  [(set_attr "cc" "clobber")
   (set (attr "length")
	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
			  (const_int 0))
		      (const_int 10)
		      (const_int 8)))])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=&r")
	(and:SI (not:SI
		  (subreg:SI 
		     (lshiftrt:QI
			(match_operand:QI 1 "bit_operand" "Ur")
			(match_operand:QI 2 "const_int_operand" "n")) 0))
		(const_int 1)))]
  "1"
  "* return output_simode_bld (1, 0, operands);"
  [(set_attr "cc" "clobber")
   (set (attr "length")
	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
			  (const_int 0))
		      (const_int 10)
		      (const_int 8)))])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=&r")
	(zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
				 (match_operand:HI 3 "p_operand" "P"))
			 (const_int 1)
			 (match_operand:HI 2 "const_int_operand" "n")))]
  "(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
  "sub.w	%0,%0\;bild	%Z2,%Y1\;bst	#0,%X0"
  [(set_attr "cc" "clobber")
   (set_attr "length" "8")])

(define_expand "insv"
  [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
			 (match_operand:HI 1 "general_operand" "")
			 (match_operand:HI 2 "general_operand" ""))
	(match_operand:HI 3 "general_operand" ""))]
  "TARGET_H8300"
  "
{
  /* We only have single bit bitfield instructions.  */
  if (INTVAL (operands[1]) != 1)
    FAIL;

  /* For now, we don't allow memory operands.  */
  if (GET_CODE (operands[0]) == MEM
      || GET_CODE (operands[3]) == MEM)
    FAIL;
}")

(define_insn ""
  [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
			 (const_int 1)
			 (match_operand:HI 1 "immediate_operand" "n"))
	(match_operand:HI 2 "register_operand" "r"))]
  ""
  "bld	#0,%R2\;bst	%Z1,%Y0 ; i1"
  [(set_attr "cc" "clobber")
   (set_attr "length" "4")])

(define_expand "extzv"
  [(set (match_operand:HI 0 "register_operand" "") 
	(zero_extract:HI (match_operand:HI 1 "bit_operand" "")
			 (match_operand:HI 2 "general_operand" "")
			 (match_operand:HI 3 "general_operand" "")))]
  "TARGET_H8300"
  "
{
  /* We only have single bit bitfield instructions.  */