i860.md

gcc-2.95.3 Linux下最常用的C编译器

}")

;(The i860 instruction set doesn't allow an immediate second operand in
; a subtraction.)
(define_insn "negsi2"
  [(set (match_operand:SI 0 "general_operand" "=r")
	(neg:SI (match_operand:SI 1 "arith_operand" "r")))]
  ""
  "*
{
  CC_STATUS_PARTIAL_INIT;
  return \"subu %?r0,%1,%0\";
}")

(define_insn "one_cmplsi2"
  [(set (match_operand:SI 0 "general_operand" "=r")
	(not:SI (match_operand:SI 1 "arith_operand" "r")))]
  ""
  "*
{
  CC_STATUS_PARTIAL_INIT;
  return \"subu -1,%1,%0\";
}")

;; Floating point arithmetic instructions.

(define_insn "adddf3"
  [(set (match_operand:DF 0 "register_operand" "=f")
	(plus:DF (match_operand:DF 1 "register_operand" "f")
		 (match_operand:DF 2 "register_operand" "f")))]
  ""
  "fadd.dd %1,%2,%0")

(define_insn "addsf3"
  [(set (match_operand:SF 0 "register_operand" "=f")
	(plus:SF (match_operand:SF 1 "register_operand" "f")
		 (match_operand:SF 2 "register_operand" "f")))]
  ""
  "fadd.ss %1,%2,%0")

(define_insn "subdf3"
  [(set (match_operand:DF 0 "register_operand" "=f")
	(minus:DF (match_operand:DF 1 "register_operand" "f")
		  (match_operand:DF 2 "register_operand" "f")))]
  ""
  "fsub.dd %1,%2,%0")

(define_insn "subsf3"
  [(set (match_operand:SF 0 "register_operand" "=f")
	(minus:SF (match_operand:SF 1 "register_operand" "f")
		  (match_operand:SF 2 "register_operand" "f")))]
  ""
  "fsub.ss %1,%2,%0")

(define_insn "muldf3"
  [(set (match_operand:DF 0 "register_operand" "=f")
	(mult:DF (match_operand:DF 1 "register_operand" "f")
		 (match_operand:DF 2 "register_operand" "f")))]
  ""
  "fmul.dd %1,%2,%0")

(define_insn "mulsf3"
  [(set (match_operand:SF 0 "register_operand" "=f")
	(mult:SF (match_operand:SF 1 "register_operand" "f")
		 (match_operand:SF 2 "register_operand" "f")))]
  ""
  "fmul.ss %1,%2,%0")

(define_insn "negdf2"
  [(set (match_operand:DF 0 "register_operand" "=f")
	(neg:DF (match_operand:DF 1 "register_operand" "f")))]
  ""
  "fsub.dd %?f0,%1,%0")

(define_insn "negsf2"
  [(set (match_operand:SF 0 "register_operand" "=f")
	(neg:SF (match_operand:SF 1 "register_operand" "f")))]
  ""
  "fsub.ss %?f0,%1,%0")

(define_insn "divdf3"
  [(set (match_operand:DF 0 "register_operand" "=&f")
	(div:DF (match_operand:DF 1 "register_operand" "f")
		 (match_operand:DF 2 "register_operand" "f")))
   (clobber (match_scratch:DF 3 "=&f"))
   (clobber (match_scratch:DF 4 "=&f"))]
  ""
  "*
{
  CC_STATUS_PARTIAL_INIT;
  if (((cc_prev_status.flags & CC_KNOW_HI_R31) == 0)
      || (cc_prev_status.flags & CC_HI_R31_ADJ)
      || (cc_prev_status.mdep != CONST2_RTX (SFmode)))
    {
      cc_status.flags |= CC_KNOW_HI_R31;
      cc_status.flags &= ~CC_HI_R31_ADJ;
      cc_status.mdep = CONST2_RTX (SFmode); 
      return \"frcp.dd %2,%3\;fmul.dd %2,%3,%0\;fmov.dd %?f0,%4\;\\\
orh 0x4000,%?r0,%?r31\;ixfr %?r31,%R4\;fsub.dd %4,%0,%0\;\\\
fmul.dd %3,%0,%3\;fmul.dd %2,%3,%0\;fsub.dd %4,%0,%0\;\\\
fmul.dd %3,%0,%3\;fmul.dd %2,%3,%0\;fsub.dd %4,%0,%0\;\\\
fmul.dd %3,%1,%3\;fmul.dd %0,%3,%0\";
    }
  else
    return \"frcp.dd %2,%3\;fmul.dd %2,%3,%0\;fmov.dd %?f0,%4\;\\\
ixfr %?r31,%R4\;fsub.dd %4,%0,%0\;\\\
fmul.dd %3,%0,%3\;fmul.dd %2,%3,%0\;fsub.dd %4,%0,%0\;\\\
fmul.dd %3,%0,%3\;fmul.dd %2,%3,%0\;fsub.dd %4,%0,%0\;\\\
fmul.dd %3,%1,%3\;fmul.dd %0,%3,%0\";
}")

(define_insn "divsf3"
  [(set (match_operand:SF 0 "register_operand" "=&f")
	(div:SF (match_operand:SF 1 "register_operand" "f")
		 (match_operand:SF 2 "register_operand" "f")))
   (clobber (match_scratch:SF 3 "=&f"))
   (clobber (match_scratch:SF 4 "=&f"))]
  ""
  "*
{
  CC_STATUS_PARTIAL_INIT;
  if (((cc_prev_status.flags & CC_KNOW_HI_R31) == 0)
      || (cc_prev_status.flags & CC_HI_R31_ADJ)
      || (cc_prev_status.mdep != CONST2_RTX (SFmode)))
    {
      cc_status.flags |= CC_KNOW_HI_R31;
      cc_status.flags &= ~CC_HI_R31_ADJ;
      cc_status.mdep = CONST2_RTX (SFmode);
      output_asm_insn (\"orh 0x4000,%?r0,%?r31\", operands);
    }
  return \"ixfr %?r31,%4\;frcp.ss %2,%0\;\\\
fmul.ss %2,%0,%3\;fsub.ss %4,%3,%3\;fmul.ss %0,%3,%0\;\\\
fmul.ss %2,%0,%3\;fsub.ss %4,%3,%3\;\\\
fmul.ss %1,%0,%4\;fmul.ss %3,%4,%0\";
}")

;; Shift instructions

;; Optimized special case of shifting.
;; Must precede the general case.

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
		     (const_int 24)))]
  ""
  "*
{
  if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
    {
      CC_STATUS_INIT;
      cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
      cc_status.mdep = XEXP (operands[1], 0);
      return \"orh %h1,%?r0,%?r31\;ld.b %L1(%?r31),%0\";
    }
  return \"ld.b %1,%0\";
}")


;;- arithmetic shift instructions
(define_insn "ashlsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ashift:SI (match_operand:SI 1 "register_operand" "r")
		   (match_operand:SI 2 "shift_operand" "rn")))]
  ""
  "*
{
  return \"shl %2,%1,%0\";
}")

(define_insn "ashlhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(ashift:HI (match_operand:HI 1 "register_operand" "r")
		   (match_operand:HI 2 "shift_operand" "rn")))]
  ""
  "*
{
  return \"shl %2,%1,%0\";
}")

(define_insn "ashlqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(ashift:QI (match_operand:QI 1 "register_operand" "r")
		   (match_operand:QI 2 "shift_operand" "rn")))]
  ""
  "*
{
  return \"shl %2,%1,%0\";
}")

(define_insn "ashrsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
		     (match_operand:SI 2 "shift_operand" "rn")))]
  ""
  "*
{
  return \"shra %2,%1,%0\";
}")

(define_insn "lshrsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
		     (match_operand:SI 2 "shift_operand" "rn")))]
  ""
  "*
{
  return \"shr %2,%1,%0\";
}")

;; Unconditional and other jump instructions

(define_insn "jump"
  [(set (pc) (label_ref (match_operand 0 "" "")))]
  ""
  "*
{
  return \"br %l0\;nop\";
}")

;; Here are two simple peepholes which fill the delay slot of
;; an unconditional branch.

(define_peephole
  [(set (match_operand:SI 0 "register_operand" "=rf")
	(match_operand:SI 1 "single_insn_src_p" "gfG"))
   (set (pc) (label_ref (match_operand 2 "" "")))]
  ""
  "* return output_delayed_branch (\"br %l2\", operands, insn);")

(define_peephole
  [(set (match_operand:SI 0 "memory_operand" "=m")
	(match_operand:SI 1 "reg_or_0_operand" "rfJ"))
   (set (pc) (label_ref (match_operand 2 "" "")))]
  ""
  "* return output_delayed_branch (\"br %l2\", operands, insn);")

(define_insn "tablejump"
  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
   (use (label_ref (match_operand 1 "" "")))]
  ""
  "bri %0\;nop")

(define_peephole
  [(set (match_operand:SI 0 "memory_operand" "=m")
	(match_operand:SI 1 "reg_or_0_operand" "rfJ"))
   (set (pc) (match_operand:SI 2 "register_operand" "r"))
   (use (label_ref (match_operand 3 "" "")))]
  ""
  "* return output_delayed_branch (\"bri %2\", operands, insn);")

;;- jump to subroutine
(define_expand "call"
  [(call (match_operand:SI 0 "memory_operand" "m")
	 (match_operand 1 "" "i"))]
  ;; operand[2] is next_arg_register
  ""
  "
{
  /* Make sure the address is just one reg and will stay that way.  */
  if (! call_insn_operand (operands[0], QImode))
    operands[0]
      = change_address (operands[0], VOIDmode,
			copy_to_mode_reg (Pmode, XEXP (operands[0], 0)));
  if (INTVAL (operands[1]) > 0)
    {
      emit_move_insn (arg_pointer_rtx, stack_pointer_rtx);
      emit_insn (gen_rtx (USE, VOIDmode, arg_pointer_rtx));
    }
}")

;;- jump to subroutine
(define_insn ""
  [(call (match_operand:SI 0 "call_insn_operand" "m")
	 (match_operand 1 "" "i"))]
  ;; operand[2] is next_arg_register
  ""
  "*
{
  /* strip the MEM.  */
  operands[0] = XEXP (operands[0], 0);
  CC_STATUS_INIT;
  if (GET_CODE (operands[0]) == REG)
    return \"calli %0\;nop\";
  return \"call %0\;nop\";
}")

(define_peephole
  [(set (match_operand:SI 0 "register_operand" "=rf")
	(match_operand:SI 1 "single_insn_src_p" "gfG"))
   (call (match_operand:SI 2 "memory_operand" "m")
	 (match_operand 3 "" "i"))]
  ;;- Don't use operand 1 for most machines.
  "! reg_mentioned_p (operands[0], operands[2])"
  "*
{
  /* strip the MEM.  */
  operands[2] = XEXP (operands[2], 0);
  if (GET_CODE (operands[2]) == REG)
    return output_delayed_branch (\"calli %2\", operands, insn);
  return output_delayed_branch (\"call %2\", operands, insn);
}")

(define_peephole
  [(set (match_operand:SI 0 "memory_operand" "=m")
	(match_operand:SI 1 "reg_or_0_operand" "rfJ"))
   (call (match_operand:SI 2 "call_insn_operand" "m")
	 (match_operand 3 "" "i"))]
  ;;- Don't use operand 1 for most machines.
  ""
  "*
{
  /* strip the MEM.  */
  operands[2] = XEXP (operands[2], 0);
  if (GET_CODE (operands[2]) == REG)
    return output_delayed_branch (\"calli %2\", operands, insn);
  return output_delayed_branch (\"call %2\", operands, insn);
}")

(define_expand "call_value"
  [(set (match_operand 0 "register_operand" "=rf")
	(call (match_operand:SI 1 "memory_operand" "m")
	      (match_operand 2 "" "i")))]
  ;; operand 3 is next_arg_register
  ""
  "
{
  /* Make sure the address is just one reg and will stay that way.  */
  if (! call_insn_operand (operands[1], QImode))
    operands[1]
      = change_address (operands[1], VOIDmode,
			copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
  if (INTVAL (operands[2]) > 0)
    {
      emit_move_insn (arg_pointer_rtx, stack_pointer_rtx);
      emit_insn (gen_rtx (USE, VOIDmode, arg_pointer_rtx));
    }
}")

(define_insn ""
  [(set (match_operand 0 "register_operand" "=rf")
	(call (match_operand:SI 1 "call_insn_operand" "m")
	      (match_operand 2 "" "i")))]
  ;; operand 3 is next_arg_register
  ""
  "*
{
  /* strip the MEM.  */
  operands[1] = XEXP (operands[1], 0);
  CC_STATUS_INIT;
  if (GET_CODE (operands[1]) == REG)
    return \"calli %1\;nop\";
  return \"call %1\;nop\";
}")

(define_peephole
  [(set (match_operand:SI 0 "register_operand" "=rf")
	(match_operand:SI 1 "single_insn_src_p" "gfG"))
   (set (match_operand 2 "" "=rf")
	(call (match_operand:SI 3 "call_insn_operand" "m")
	      (match_operand 4 "" "i")))]
  ;;- Don't use operand 4 for most machines.
  "! reg_mentioned_p (operands[0], operands[3])"
  "*
{
  /* strip the MEM.  */
  operands[3] = XEXP (operands[3], 0);
  if (GET_CODE (operands[3]) == REG)
    return output_delayed_branch (\"calli %3\", operands, insn);
  return output_delayed_branch (\"call %3\", operands, insn);
}")

(define_peephole
  [(set (match_operand:SI 0 "memory_operand" "=m")
	(match_operand:SI 1 "reg_or_0_operand" "rJf"))
   (set (match_operand 2 "" "=rf")
	(call (match_operand:SI 3 "call_insn_operand" "m")
	      (match_operand 4 "" "i")))]
  ;;- Don't use operand 4 for most machines.
  ""
  "*
{
  /* strip the MEM.  */
  operands[3] = XEXP (operands[3], 0);
  if (GET_CODE (operands[3]) == REG)
    return output_delayed_branch (\"calli %3\", operands, insn);
  return output_delayed_branch (\"call %3\", operands, insn);
}")

;; Call subroutine returning any type.

(define_expand "untyped_call"
  [(parallel [(call (match_operand 0 "" "")
		    (const_int 0))
	      (match_operand 1 "" "")
	      (match_operand 2 "" "")])]
  ""
  "
{
  int i;

  emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));

  for (i = 0; i < XVECLEN (operands[2], 0); i++)
    {
      rtx set = XVECEXP (operands[2], 0, i);
      emit_move_insn (SET_DEST (set), SET_SRC (set));
    }

  /* The optimizer does not know that the call sets the function value
     registers we stored in the result block.  We avoid problems by
     claiming that all hard registers are used and clobbered at this
     point.  */
  emit_insn (gen_blockage ());

  DONE;
}")

;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
;; all of memory.  This blocks insns from being moved across this point.

(define_insn "blockage"
  [(unspec_volatile [(const_int 0)] 0)]
  ""
  "")

(define_insn "nop"
  [(const_int 0)]
  ""
  "nop")

(define_insn "indirect_jump"
  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
  ""
  "bri %0")

;;
;; A special insn that does the work to get setup just
;; before a table jump.
;;
(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
			 (label_ref (match_operand 2 "" "")))))]
  ""
  "*
{
  CC_STATUS_INIT;
  return \"orh %H2,%?r0,%?r31\;or %L2,%?r31,%?r31\;ld.l %?r31(%1),%0\";
}")
  
(define_peephole
  [(set (match_operand:SI 0 "register_operand" "=rf")
	(match_operand:SI 1 "single_insn_src_p" "gfG"))
   (set (pc) (match_operand:SI 2 "register_operand" "r"))
   (use (label_ref (match_operand 3 "" "")))]
  "REGNO (operands[0]) != REGNO (operands[2])"
  "* return output_delayed_branch (\"bri %2\", operands, insn);")