i860.md

gcc-2.95.3 Linux下最常用的C编译器

    }
  return \"orh %H1,%?r0,%0\;or %L1,%0,%0\";
}")
 
(define_insn "movhi"
  [(set (match_operand:HI 0 "general_operand" "=r,m,!*f,!r")
	(match_operand:HI 1 "general_operand" "rmi,rJ,rJ*f,*f"))]
  ""
  "*
{
  if (GET_CODE (operands[0]) == MEM)
    {
      if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
	return output_store (operands);
      return \"st.s %r1,%0\";
    }
  if (GET_CODE (operands[1]) == MEM)
    {
      if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
	return output_load (operands);
      return \"ld.s %1,%0\";
    }
  if (FP_REG_P (operands[1]) && FP_REG_P (operands[0]))
    return \"fmov.ss %1,%0\";
  if (FP_REG_P (operands[1]))
    return \"fxfr %1,%0\";
  if (FP_REG_P (operands[0]) && operands[1] == const0_rtx)
    return \"fmov.ss %?f0,%0\";
  if (FP_REG_P (operands[0]))
    return \"ixfr %1,%0\";

  if (GET_CODE (operands[1]) == REG)
    return \"shl %?r0,%1,%0\";

  CC_STATUS_PARTIAL_INIT;

  return \"or %L1,%?r0,%0\";
}")

(define_insn "movqi"
  [(set (match_operand:QI 0 "general_operand" "=r,m,!*f,!r")
	(match_operand:QI 1 "general_operand" "rmi,rJ,rJ*f,*f"))]
  ""
  "*
{
  if (GET_CODE (operands[0]) == MEM)
    {
      if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
	return output_store (operands);
      return \"st.b %r1,%0\";
    }
  if (GET_CODE (operands[1]) == MEM)
    {
      if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
	return output_load (operands);
      return \"ld.b %1,%0\";
    }
  if (FP_REG_P (operands[1]) && FP_REG_P (operands[0]))
    return \"fmov.ss %1,%0\";
  if (FP_REG_P (operands[1]))
    return \"fxfr %1,%0\";
  if (FP_REG_P (operands[0]) && operands[1] == const0_rtx)
    return \"fmov.ss %?f0,%0\";
  if (FP_REG_P (operands[0]))
    return \"ixfr %1,%0\";

  if (GET_CODE (operands[1]) == REG)
    return \"shl %?r0,%1,%0\";

  CC_STATUS_PARTIAL_INIT;

  return \"or %L1,%?r0,%0\";
}")

;; The definition of this insn does not really explain what it does,
;; but it should suffice
;; that anything generated as this insn will be recognized as one
;; and that it won't successfully combine with anything.
(define_expand "movstrsi"
  [(parallel [(set (match_operand:BLK 0 "general_operand" "")
		   (match_operand:BLK 1 "general_operand" ""))
	      (use (match_operand:SI 2 "nonmemory_operand" ""))
	      (use (match_operand:SI 3 "immediate_operand" ""))
	      (clobber (match_dup 4))
	      (clobber (match_dup 5))
	      (clobber (match_dup 6))
	      (clobber (match_dup 7))
	      (clobber (match_dup 8))])]
  ""
  "
{
  operands[4] = gen_reg_rtx (SImode);
  operands[5] = gen_reg_rtx (SImode);
  operands[6] = gen_reg_rtx (SImode);
  operands[7] = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
  operands[8] = copy_to_mode_reg (SImode, XEXP (operands[1], 0));

  operands[0] = change_address (operands[0], VOIDmode, operands[7]);
  operands[1] = change_address (operands[1], VOIDmode, operands[8]);
}")

(define_insn ""
  [(set (mem:BLK (match_operand:SI 0 "register_operand" "r"))
	(mem:BLK (match_operand:SI 1 "register_operand" "r")))
   (use (match_operand:SI 2 "general_operand" "rn"))
   (use (match_operand:SI 3 "immediate_operand" "i"))
   (clobber (match_operand:SI 4 "register_operand" "=r"))
   (clobber (match_operand:SI 5 "register_operand" "=r"))
   (clobber (match_operand:SI 6 "register_operand" "=r"))
   (clobber (match_dup 0))
   (clobber (match_dup 1))]
  ""
  "* return output_block_move (operands);")

;; Floating point move insns

;; This pattern forces (set (reg:DF ...) (const_double ...))
;; to be reloaded by putting the constant into memory.
;; It must come before the more general movdf pattern.
(define_insn ""
  [(set (match_operand:DF 0 "general_operand" "=r,f,o")
	(match_operand:DF 1 "" "mG,m,G"))]
  "GET_CODE (operands[1]) == CONST_DOUBLE"
  "*
{
  if (FP_REG_P (operands[0]) || operands[1] == CONST0_RTX (DFmode))
    return output_fp_move_double (operands);
  return output_move_double (operands);
}")

(define_insn "movdf"
  [(set (match_operand:DF 0 "general_operand" "=*rm,*r,?f,?*rm")
	(match_operand:DF 1 "general_operand" "*r,m,*rfmG,f"))]
  ""
  "*
{
  if (GET_CODE (operands[0]) == MEM
      && CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
    return output_store (operands);
  if (GET_CODE (operands[1]) == MEM
      && CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
    return output_load (operands);

  if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
    return output_fp_move_double (operands);
  return output_move_double (operands);
}")

(define_insn "movdi"
  [(set (match_operand:DI 0 "general_operand" "=rm,r,?f,?rm")
	(match_operand:DI 1 "general_operand" "r,miF,rfmG,f"))]
  ""
  "*
{
  if (GET_CODE (operands[0]) == MEM
      && CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
    return output_store (operands);
  if (GET_CODE (operands[1]) == MEM
      && CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
    return output_load (operands);

  /* ??? How can we have a DFmode arg here with DImode above? */
  if (FP_REG_P (operands[0]) && operands[1] == CONST0_RTX (DFmode))
    return \"fmov.dd %?f0,%0\";

  if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
    return output_fp_move_double (operands);
  return output_move_double (operands);
}")

;; The alternative m/r is separate from m/f
;; The first alternative is separate from the second for the same reason.
(define_insn "movsf"
  [(set (match_operand:SF 0 "general_operand" "=*rf,*rf,*r,m,m")
	(match_operand:SF 1 "general_operand" "*r,fmG,F,*r,f"))]
  ""
  "*
{
  if (GET_CODE (operands[0]) == MEM
      && CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
    return output_store (operands);
  if (GET_CODE (operands[1]) == MEM
      && CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
    return output_load (operands);
  if (FP_REG_P (operands[0]))
    {
      if (FP_REG_P (operands[1]))
	return \"fmov.ss %1,%0\";
      if (GET_CODE (operands[1]) == REG)
	return \"ixfr %1,%0\";
      if (operands[1] == CONST0_RTX (SFmode))
        return \"fmov.ss %?f0,%0\";
      if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
	{
	  if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
		 && (cc_prev_status.flags & CC_HI_R31_ADJ)
		 && cc_prev_status.mdep == XEXP(operands[1],0)))
	    {
	      CC_STATUS_INIT;
	      cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
	      cc_status.mdep = XEXP (operands[1], 0);
	      return \"orh %h1,%?r0,%?r31\;fld.l %L1(%?r31),%0\";
	    }
	  return \"fld.l %L1(%?r31),%0\";
	}
      return \"fld.l %1,%0\";
    }
  if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
    {
      if (GET_CODE (operands[0]) == REG && FP_REG_P (operands[1]))
	return \"fxfr %1,%0\";
      if (GET_CODE (operands[0]) == REG)
	{
	  CC_STATUS_PARTIAL_INIT;
	  if (GET_CODE (operands[1]) == CONST_DOUBLE)
	    {
	      register unsigned long ul;

              ul = sfmode_constant_to_ulong (operands[1]);
	      if ((ul & 0x0000ffff) == 0)
		return \"orh %H1,%?r0,%0\";
	      if ((ul & 0xffff0000) == 0)
		return \"or %L1,%?r0,%0\";
	    }
          return \"orh %H1,%?r0,%0\;or %L1,%0,%0\";
	}
      /* Now operand 0 must be memory.
         If operand 1 is CONST_DOUBLE, its value must be 0.  */
      if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
	{
	  if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
		 && (cc_prev_status.flags & CC_HI_R31_ADJ)
		 && XEXP (operands[0], 0) == cc_prev_status.mdep))
	    {
	      CC_STATUS_INIT;
	      cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
	      cc_status.mdep = XEXP (operands[0], 0);
	      output_asm_insn (\"orh %h0,%?r0,%?r31\", operands);
	    }
	  return \"fst.l %r1,%L0(%?r31)\";
	}
      return \"fst.l %r1,%0\";
    }
  if (GET_CODE (operands[0]) == MEM)
    return \"st.l %r1,%0\";
  if (GET_CODE (operands[1]) == MEM)
    return \"ld.l %1,%0\";
  if (operands[1] == CONST0_RTX (SFmode))
    return \"shl %?r0,%?r0,%0\";
  return \"mov %1,%0\";
}")

;; Special load insns for REG+REG addresses.
;; Such addresses are not "legitimate" because st rejects them.

(define_insn ""
  [(set (match_operand:DF 0 "register_operand" "=rf")
	(match_operand:DF 1 "indexed_operand" "m"))]
  ""
  "*
{
  if (FP_REG_P (operands[0]))
    return output_fp_move_double (operands);
  return output_move_double (operands);
}")

(define_insn ""
  [(set (match_operand:SF 0 "register_operand" "=rf")
	(match_operand:SF 1 "indexed_operand" "m"))]
  ""
  "*
{
  if (FP_REG_P (operands[0]))
    return \"fld.l %1,%0\";
  return \"ld.l %1,%0\";
}")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=rf")
	(match_operand:SI 1 "indexed_operand" "m"))]
  ""
  "*
{
  if (FP_REG_P (operands[0]))
    return \"fld.l %1,%0\";
  return \"ld.l %1,%0\";
}")

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=r")
	(match_operand:HI 1 "indexed_operand" "m"))]
  ""
  "ld.s %1,%0")

(define_insn ""
  [(set (match_operand:QI 0 "register_operand" "=r")
	(match_operand:QI 1 "indexed_operand" "m"))]
  ""
  "ld.b %1,%0")

;; Likewise for floating-point store insns.

(define_insn ""
  [(set (match_operand:DF 0 "indexed_operand" "=m")
	(match_operand:DF 1 "register_operand" "f"))]
  ""
  "fst.d %1,%0")

(define_insn ""
  [(set (match_operand:SF 0 "indexed_operand" "=m")
	(match_operand:SF 1 "register_operand" "f"))]
  ""
  "fst.l %1,%0")

;;- truncation instructions
(define_insn "truncsiqi2"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(truncate:QI
	 (match_operand:SI 1 "register_operand" "r")))]
  ""
  "*
{
  if (GET_CODE (operands[0]) == MEM)
    if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
      {
	if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
	       && (cc_prev_status.flags & CC_HI_R31_ADJ)
	       && XEXP (operands[0], 0) == cc_prev_status.mdep))
	  {
	    CC_STATUS_INIT;
	    cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
	    cc_status.mdep = XEXP (operands[0], 0);
	    output_asm_insn (\"orh %h0,%?r0,%?r31\", operands);
	  }
	return \"st.b %1,%L0(%?r31)\";
      }
    else
      return \"st.b %1,%0\";
  return \"shl %?r0,%1,%0\";
}")

(define_insn "trunchiqi2"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(truncate:QI
	 (match_operand:HI 1 "register_operand" "r")))]
  ""
  "*
{
  if (GET_CODE (operands[0]) == MEM)
    if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
      {
	if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
	       && (cc_prev_status.flags & CC_HI_R31_ADJ)
	       && XEXP (operands[0], 0) == cc_prev_status.mdep))
	  {
	    CC_STATUS_INIT;
	    cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
	    cc_status.mdep = XEXP (operands[0], 0);
	    output_asm_insn (\"orh %h0,%?r0,%?r31\", operands);
	  }
	return \"st.b %1,%L0(%?r31)\";
      }
    else
      return \"st.b %1,%0\";
  return \"shl %?r0,%1,%0\";
}")

(define_insn "truncsihi2"
  [(set (match_operand:HI 0 "general_operand" "=g")
	(truncate:HI
	 (match_operand:SI 1 "register_operand" "r")))]
  ""
  "*
{
  if (GET_CODE (operands[0]) == MEM)
    if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
      {
	if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
	       && (cc_prev_status.flags & CC_HI_R31_ADJ)
	       && XEXP (operands[0], 0) == cc_prev_status.mdep))
	  {
	    CC_STATUS_INIT;
	    cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
	    cc_status.mdep = XEXP (operands[0], 0);
	    output_asm_insn (\"orh %h0,%?r0,%?r31\", operands);
	  }
	return \"st.s %1,%L0(%?r31)\";
      }
    else
      return \"st.s %1,%0\";
  return \"shl %?r0,%1,%0\";
}")

;;- zero extension instructions

(define_insn "zero_extendhisi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(zero_extend:SI
	 (match_operand:HI 1 "register_operand" "r")))]
  ""
  "*
{
  CC_STATUS_PARTIAL_INIT;
  return \"and 0xffff,%1,%0\";
}")

(define_insn "zero_extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(zero_extend:HI
	 (match_operand:QI 1 "register_operand" "r")))]
  ""
  "*
{
  CC_STATUS_PARTIAL_INIT;
  return \"and 0xff,%1,%0\";
}")

(define_insn "zero_extendqisi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(zero_extend:SI
	 (match_operand:QI 1 "register_operand" "r")))]
  ""
  "*
{
  CC_STATUS_PARTIAL_INIT;
  return \"and 0xff,%1,%0\";
}")

;; Sign extension instructions.

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(sign_extend:SI
	 (match_operand:HI 1 "indexed_operand" "m")))]
  ""
  "ld.s %1,%0")

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=r")
	(sign_extend:HI
	 (match_operand:QI 1 "indexed_operand" "m")))]
  ""
  "ld.b %1,%0")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(sign_extend:SI
	 (match_operand:QI 1 "indexed_operand" "m")))]
  ""
  "ld.b %1,%0")

(define_insn "extendhisi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(sign_extend:SI
	 (match_operand:HI 1 "nonimmediate_operand" "mr")))]
  ""
  "*
{
  if (REG_P (operands[1]))
    return \"shl 16,%1,%0\;shra 16,%0,%0\";
  if (GET_CODE (operands[1]) == CONST_INT)
    abort ();
  if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))