romp.h

gcc-2.95.3 Linux下最常用的C编译器

/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
   and check its validity for a certain class.
   We have two alternate definitions for each of them.
   The usual definition accepts all pseudo regs; the other rejects
   them unless they have been allocated suitable hard regs.
   The symbol REG_OK_STRICT causes the latter definition to be used.

   Most source files want to accept pseudo regs in the hope that
   they will get allocated to the class that the insn wants them to be in.
   Source files for reload pass need to be strict.
   After reload, it makes no difference, since pseudo regs have
   been eliminated by then.  */

#ifndef REG_OK_STRICT

/* Nonzero if X is a hard reg that can be used as an index
   or if it is a pseudo reg.  */
#define REG_OK_FOR_INDEX_P(X) 0
/* Nonzero if X is a hard reg that can be used as a base reg
   or if it is a pseudo reg.  */
#define REG_OK_FOR_BASE_P(X)		\
  (REGNO (X) != 0 && (REGNO (X) < 17 || REGNO (X) >= FIRST_PSEUDO_REGISTER))

#else

/* Nonzero if X is a hard reg that can be used as an index.  */
#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
/* Nonzero if X is a hard reg that can be used as a base reg.  */
#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))

#endif

/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
   that is a valid memory address for an instruction.
   The MODE argument is the machine mode for the MEM expression
   that wants to use this address.

   On the ROMP, a legitimate address is either a legitimate constant,
   a register plus a legitimate constant, or a register.  See the
   discussion at the LEGITIMATE_ADDRESS_CONSTANT_P macro.  */
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)				\
{ if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))			\
    goto ADDR;								\
  if (GET_CODE (X) != CONST_INT && LEGITIMATE_ADDRESS_CONSTANT_P (X))	\
    goto ADDR;								\
  if (GET_CODE (X) == PLUS						\
      && GET_CODE (XEXP (X, 0)) == REG					\
      && REG_OK_FOR_BASE_P (XEXP (X, 0))				\
      && LEGITIMATE_ADDRESS_CONSTANT_P (XEXP (X, 1)))			\
	goto ADDR;							\
  if (GET_CODE (X) == PLUS						\
      && GET_CODE (XEXP (X, 0)) == REG					\
      && REG_OK_FOR_BASE_P (XEXP (X, 0))				\
      && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0)			\
      && (((MODE) != DFmode && (MODE) != DImode)			\
	  || (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4))))		\
	goto ADDR;							\
}

/* Try machine-dependent ways of modifying an illegitimate address
   to be legitimate.  If we find one, return the new, valid address.
   This macro is used in only one place: `memory_address' in explow.c.

   OLDX is the address as it was before break_out_memory_refs was called.
   In some cases it is useful to look at this to decide what needs to be done.

   MODE and WIN are passed so that this macro can use
   GO_IF_LEGITIMATE_ADDRESS.

   It is always safe for this macro to do nothing.  It exists to recognize
   opportunities to optimize the output.

   On ROMP, check for the sum of a register with a constant
   integer that is out of range.  If so, generate code to add the
   constant with the low-order 16 bits masked to the register and force
   this result into another register (this can be done with `cau').
   Then generate an address of REG+(CONST&0xffff), allowing for the 
   possibility of bit 16 being a one.

   If the register is not OK for a base register, abort.  */

#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)			\
{ if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG	\
    && GET_CODE (XEXP (X, 1)) == CONST_INT			\
    && (unsigned) (INTVAL (XEXP (X, 1)) + 0x8000) >= 0x10000)	\
    { int high_int, low_int;					\
      if (! REG_OK_FOR_BASE_P (XEXP (X, 0)))			\
	abort ();						\
      high_int = INTVAL (XEXP (X, 1)) >> 16;			\
      low_int = INTVAL (XEXP (X, 1)) & 0xffff;			\
      if (low_int & 0x8000)					\
	high_int += 1, low_int |= 0xffff0000;			\
      (X) = gen_rtx (PLUS, SImode,				\
		     force_operand				\
		     	(gen_rtx (PLUS, SImode, XEXP (X, 0), \
				  GEN_INT (high_int << 16)), 0),\
		     GEN_INT (low_int));			\
    }								\
}

/* Go to LABEL if ADDR (a legitimate address expression)
   has an effect that depends on the machine mode it is used for.

   On the ROMP this is true only if the address is valid with a zero offset
   but not with an offset of four (this means it cannot be used as an
   address for DImode or DFmode).  Since we know it is valid, we just check
   for an address that is not valid with an offset of four.  */

#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)		\
{ if (GET_CODE (ADDR) == PLUS					\
      && ! LEGITIMATE_ADDRESS_CONSTANT_P (XEXP (ADDR, 1))	\
      && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 4))	\
    goto LABEL;							\
}

/* Define this if some processing needs to be done immediately before
   emitting code for an insn.

   This is used on the ROMP, to compensate for a bug in the floating-point
   code.  When a floating-point operation is done with the first and third
   operands both the same floating-point register, it will generate bad code
   for the MC68881.  So we must detect this.  If it occurs, we patch the 
   first operand to be fr0 and insert a move insn to move it to the desired
   destination.  */
#define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS)			\
  { rtx op0, op1, op2, operation, tem;					\
    if (NOPERANDS >= 3	&& get_attr_type (INSN) == TYPE_FP)		\
      {									\
	op0 = OPERANDS[0];						\
	operation = OPERANDS[1];					\
	if (float_conversion (operation, VOIDmode))			\
	  operation = XEXP (operation, 0);				\
        if (float_binary (operation, VOIDmode))				\
	  {								\
	    op1 = XEXP (operation, 0), op2 = XEXP (operation, 1);	\
	    if (float_conversion (op1, VOIDmode))			\
	      op1 = XEXP (op1, 0);					\
	    if (float_conversion (op2, VOIDmode))			\
	      op2 = XEXP (op2, 0);					\
	    if (rtx_equal_p (op0, op2)					\
		&& (GET_CODE (operation) == PLUS			\
		    || GET_CODE (operation) == MULT))			\
	      tem = op1, op1 = op2, op2 = tem;				\
	    if (GET_CODE (op0) == REG && FP_REGNO_P (REGNO (op0))	\
		&& GET_CODE (op2) == REG && FP_REGNO_P (REGNO (op2))	\
		&& REGNO (op0) == REGNO (op2))				\
	      {								\
		tem = gen_rtx (REG, GET_MODE (op0), 17);		\
		emit_insn_after (gen_move_insn (op0, tem), INSN);	\
		SET_DEST (XVECEXP (PATTERN (INSN), 0, 0)) = tem; 	\
		OPERANDS[0] = tem;					\
	      }								\
	  }								\
      }									\
  }

/* Specify the machine mode that this machine uses
   for the index in the tablejump instruction.  */
#define CASE_VECTOR_MODE SImode

/* Define as C expression which evaluates to nonzero if the tablejump
   instruction expects the table to contain offsets from the address of the
   table.
   Do not define this if the table should contain absolute addresses. */
/* #define CASE_VECTOR_PC_RELATIVE 1 */

/* Specify the tree operation to be used to convert reals to integers.  */
#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR

/* This is the kind of divide that is easiest to do in the general case.  */
#define EASY_DIV_EXPR TRUNC_DIV_EXPR

/* Define this as 1 if `char' should by default be signed; else as 0.  */
#define DEFAULT_SIGNED_CHAR 0

/* This flag, if defined, says the same insns that convert to a signed fixnum
   also convert validly to an unsigned one.

   We actually lie a bit here as overflow conditions are different.  But
   they aren't being checked anyway.  */

#define FIXUNS_TRUNC_LIKE_FIX_TRUNC

/* Max number of bytes we can move from memory to memory
   in one reasonably fast instruction.  */
#define MOVE_MAX 4

/* Nonzero if access to memory by bytes is no faster than for words.
   Also non-zero if doing byte operations (specifically shifts) in registers
   is undesirable.  */
#define SLOW_BYTE_ACCESS 1

/* Define if operations between registers always perform the operation
   on the full register even if a narrower mode is specified.  */
#define WORD_REGISTER_OPERATIONS

/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
   will either zero-extend or sign-extend.  The value of this macro should
   be the code that says which one of the two operations is implicitly
   done, NIL if none.  */
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND

/* This is BSD, so it wants DBX format.  */
#define DBX_DEBUGGING_INFO

/* Define the letter code used in a stabs entry for parameters passed
   with the register attribute.

   GCC's default value, 'P', is used by dbx to refers to an external
   procedure. The section 5 manual page for dbx implies that 'R' would be the
   right letter, but dbx 1.5 has a bug in it that precludes its use.
   Probably that is why neither hc or pcc use this. pcc puts in two
   stabs entries: one for the parameter location and one for the register
   location. The letter `r' (register)
   would be okay, but it loses parameter attribute of the stabs entry.  */
#define DBX_REGPARM_STABS_LETTER 'R'

/* A C expression for the integer offset value of an automatic variable
   (N_LSYM) having address X (an RTX). This gets used in .stabs entries
   for the local variables. Compare with the default definition.  */
extern int romp_debugger_auto_correction();
#define DEBUGGER_AUTO_OFFSET(X)                        \
  (GET_CODE (X) == PLUS                                \
   ? romp_debugger_auto_correction (INTVAL (XEXP (X, 1)) ) \
   : 0 )

/* A C expression for the integer offset value of an argument (N_PSYM)
   having address X (an RTX).  The nominal offset is OFFSET.  */
extern int romp_debugger_arg_correction();
#define DEBUGGER_ARG_OFFSET(OFFSET, X)             \
  romp_debugger_arg_correction (OFFSET);

/* We don't have GAS for the RT yet, so don't write out special
   .stabs in cc1plus.  */
   
#define FASCIST_ASSEMBLER

/* Do not break .stabs pseudos into continuations.  */
#define DBX_CONTIN_LENGTH 0

/* Don't try to use the `x' type-cross-reference character in DBX data.
   Also has the consequence of putting each struct, union or enum
   into a separate .stabs, containing only cross-refs to the others.  */
#define DBX_NO_XREFS

/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
   is done just by pretending it is already truncated.  */
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1

/* Specify the machine mode that pointers have.
   After generation of rtl, the compiler makes no further distinction
   between pointers and any other objects of this machine mode.  */
#define Pmode SImode

/* Mode of a function address in a call instruction (for indexing purposes).

   Doesn't matter on ROMP.  */
#define FUNCTION_MODE SImode

/* Define this if addresses of constant functions
   shouldn't be put through pseudo regs where they can be cse'd.
   Desirable on machines where ordinary constants are expensive
   but a CALL with constant address is cheap.  */
#define NO_FUNCTION_CSE

/* Define this if shift instructions ignore all but the low-order
   few bits.

   This is not true on the RT since it uses the low-order 6, not 5, bits.
   At some point, this should be extended to see how to express that.  */

/* #define SHIFT_COUNT_TRUNCATED */

/* Compute the cost of computing a constant rtl expression RTX whose
   rtx-code is CODE, contained within an expression of code OUTER_CODE.
   The body of this macro is a portion of a switch statement.  If the
   code is computed here, return it with a return statement.  Otherwise,
   break from the switch.  */

#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
  case CONST_INT:						\
    if ((OUTER_CODE) == IOR && exact_log2 (INTVAL (RTX)) >= 0	\
	|| (OUTER_CODE) == AND && exact_log2 (~INTVAL (RTX)) >= 0 \
	|| (((OUTER_CODE) == PLUS || (OUTER_CODE) == MINUS)	\
	    && (unsigned int) (INTVAL (RTX) + 15) < 31)		\
	|| ((OUTER_CODE) == SET && (unsigned int) INTVAL (RTX) < 16))\
      return 0;							\
    return ((unsigned int) (INTVAL(RTX) + 0x8000) < 0x10000		\
	    || (INTVAL (RTX) & 0xffff0000) == 0) ? 0 : COSTS_N_INSNS (2);\
  case CONST:							\
  case LABEL_REF:						\
  case SYMBOL_REF:						\
    if (current_function_operand (RTX, Pmode)) return 0;	\
    return COSTS_N_INSNS (2);					\
  case CONST_DOUBLE:						\
    if ((RTX) == CONST0_RTX (GET_MODE (RTX))) return 2;		\
    return ((GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT)	\
	    ? COSTS_N_INSNS (5) : COSTS_N_INSNS (4));

/* Provide the costs of a rtl expression.  This is in the body of a
   switch on CODE. 

   References to our own data area are really references to r14, so they
   are very cheap.  Multiples and divides are very expensive.  */

#define RTX_COSTS(X,CODE,OUTER_CODE)			\
  case MEM:						\
    return current_function_operand (X, Pmode) ? 0 : COSTS_N_INSNS (2);	\
  case MULT:						\
    return (TARGET_IN_LINE_MUL && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT)\
	   ? COSTS_N_INSNS (19) : COSTS_N_INSNS (25);	\
  case DIV:						\
  case UDIV:						\
  case MOD:						\
  case UMOD:						\
    return COSTS_N_INSNS (45);

/* Compute the cost of an address.  This is meant to approximate the size
   and/or execution delay of an insn using that address.  If the cost is
   approximated by the RTL complexity, including CONST_COSTS above, as
   is usually the case for CISC machines, this macro should not be defined.
   For aggressively RISCy machines, only one insn format is allowed, so
   this macro should be a constant.  The value of this macro only matters
   for valid addresses.

   For the ROMP, everything is cost 0 except for addresses involving
   symbolic constants, which are cost 1.  */