fx80.h

gcc-2.95.3 Linux下最常用的C编译器

/* Definitions of target machine for GNU compiler.  Alliant FX version.
   Copyright (C) 1989, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
   Adapted from m68k.h by Paul Petersen ([e-mail])
   and Joe Weening ([e-mail]).

This file is part of GNU CC.

GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING.  If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA.  */


/* This file is based on m68k.h, simplified by removing support for
   the Sun FPA and other things not applicable to the Alliant.  Some
   remnants of these features remain.  */

/* Names to predefine in the preprocessor for this target machine.  */

#define CPP_PREDEFINES "-Dmc68000 -Dalliant -Dunix -Asystem(unix) -Acpu(m68k) -Amachine(m68k)"

/* Print subsidiary information on the compiler version in use.  */

#define TARGET_VERSION fprintf (stderr, " (Alliant)");

/* Run-time compilation parameters selecting different hardware
   subsets.  The Alliant IP is an mc68020.  (Older mc68010-based IPs
   are no longer supported.)  The Alliant CE is 68020-compatible, and
   also has floating point, vector and concurrency instructions.

   Although the IP doesn't have floating point, it emulates it in the
   operating system.  Using this generally is faster than running code
   compiled with -msoft-float, because the soft-float code still uses
   (simulated) FP registers and ends up emulating several fmove{s,d}
   instructions per call.  So I don't recommend using soft-float for
   any Alliant code.  -- JSW
*/

extern int target_flags;

/* Macros used in the machine description to test the flags.  */

/* Compile for a 68020 (not a 68000 or 68010).  */
#define TARGET_68020 (target_flags & 1)
/* Compile CE insns for floating point (not library calls).  */
#define TARGET_CE (target_flags & 2)
/* Compile using 68020 bitfield insns.  */
#define TARGET_BITFIELD (target_flags & 4)
/* Compile with 16-bit `int'.  */
#define TARGET_SHORT (target_flags & 040)

/* Default 3 means compile 68020 and CE instructions.  We don't use
   bitfield instructions because there appears to be a bug in the
   implementation of bfins on the CE.  */

#define TARGET_DEFAULT 3

/* Define __HAVE_CE__ in preprocessor according to the -m flags.
   This will control the use of inline FP insns in certain macros.
   Also inform the program which CPU this is for.  */

#if TARGET_DEFAULT & 02

/* -mce is the default */
#define CPP_SPEC \
"%{!msoft-float:-D__HAVE_CE__ }\
%{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}"

#else

/* -msoft-float is the default */
#define CPP_SPEC \
"%{mce:-D__HAVE_CE__ }\
%{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}"

#endif

/* Link with libg.a when debugging, for dbx's sake.  */

#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} "

/* Make the linker remove temporary labels, since the Alliant assembler
   doesn't.  */

#define LINK_SPEC "-X"

/* Every structure or union's size must be a multiple of 2 bytes.  */

#define STRUCTURE_SIZE_BOUNDARY 16

/* This is BSD, so it wants DBX format.  */

#define DBX_DEBUGGING_INFO

/* Macro to define tables used to set the flags.
   This is a list in braces of pairs in braces,
   each pair being { "NAME", VALUE }
   where VALUE is the bits to set or minus the bits to clear.
   An empty string NAME is used to identify the default VALUE.  */

#define TARGET_SWITCHES  \
  { { "68020", 5, "Generate code for a mc68020"},		\
    { "c68020", 5, "Generate code for a mc68020"},		\
    { "bitfield", 4, "Use bitfield instructions"},		\
    { "68000", -7, "Generate code for a mc68000"},		\
    { "c68000", -7, "Generate code for a mc68000"},		\
    { "soft-float", -2, "Generate software FP code"},		\
    { "nobitfield", -4, "Do not generate bitfield insns"},	\
    { "short", 040, "Use 16bit integers"},			\
    { "noshort", -040, "Use 32bit integers"},			\
    { "", TARGET_DEFAULT, NULL}}

/* target machine storage layout */

/* Define this if most significant bit is lowest numbered
   in instructions that operate on numbered bit-fields.
   This is true for 68020 insns such as bfins and bfexts.
   We make it true always by avoiding using the single-bit insns
   except in special cases with constant bit numbers.  */
#define BITS_BIG_ENDIAN 1

/* Define this if most significant byte of a word is the lowest numbered.  */
/* That is true on the 68000.  */
#define BYTES_BIG_ENDIAN 1

/* Define this if most significant word of a multiword number is the lowest
   numbered.  */
/* For 68000 we can decide arbitrarily
   since there are no machine instructions for them.  */
#define WORDS_BIG_ENDIAN 0

/* number of bits in an addressable storage unit */
#define BITS_PER_UNIT 8

/* Width in bits of a "word", which is the contents of a machine register.
   Note that this is not necessarily the width of data type `int';
   if using 16-bit ints on a 68000, this would still be 32.
   But on a machine with 16-bit registers, this would be 16.  */
#define BITS_PER_WORD 32

/* Width of a word, in units (bytes).  */
#define UNITS_PER_WORD 4

/* Width in bits of a pointer.
   See also the macro `Pmode' defined below.  */
#define POINTER_SIZE 32

/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
#define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)

/* Boundary (in *bits*) on which stack pointer should be aligned.  */
#define STACK_BOUNDARY 16

/* Allocation boundary (in *bits*) for the code of a function.  */
#define FUNCTION_BOUNDARY 16

/* Alignment of field after `int : 0' in a structure.  */
#define EMPTY_FIELD_BOUNDARY 16

/* No data type wants to be aligned rounder than this.  */
#define BIGGEST_ALIGNMENT 16

/* Set this non-zero if move instructions will actually fail to work
   when given unaligned data.  */
#define STRICT_ALIGNMENT 1

/* Define number of bits in most basic integer type.
   (If undefined, default is BITS_PER_WORD).  */

#define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)

/* Define these to avoid dependence on meaning of `int'.
   Note that WCHAR_TYPE_SIZE is used in cexp.y,
   where TARGET_SHORT is not available.  */

#define WCHAR_TYPE "long int"
#define WCHAR_TYPE_SIZE 32

/* Standard register usage.  */

/* Number of actual hardware registers.
   The hardware registers are assigned numbers for the compiler
   from 0 to just below FIRST_PSEUDO_REGISTER.
   All registers that the compiler knows about must be given numbers,
   even those that are not normally considered general registers.
   For the Alliant, we give the data registers numbers 0-7,
   the address registers numbers 010-017,
   and the floating point registers numbers 020-027.  */
#define FIRST_PSEUDO_REGISTER 24

/* 1 for registers that have pervasive standard uses
   and are not available for the register allocator.
   On the Alliant, these are a0 (argument pointer),
   a6 (frame pointer) and a7 (stack pointer).  */
#define FIXED_REGISTERS  \
 {0, 0, 0, 0, 0, 0, 0, 0, \
  1, 0, 0, 0, 0, 0, 1, 1, \
  0, 0, 0, 0, 0, 0, 0, 0  }

/* 1 for registers not available across function calls.
   These must include the FIXED_REGISTERS and also any
   registers that can be used without being saved.
   The latter must include the registers where values are returned
   and the register where structure-value addresses are passed.
   Aside from that, you can include as many other registers as you like.
   The Alliant calling sequence allows a function to use any register,
   so we include them all here.  */

#define CALL_USED_REGISTERS \
 {1, 1, 1, 1, 1, 1, 1, 1, \
  1, 1, 1, 1, 1, 1, 1, 1, \
  1, 1, 1, 1, 1, 1, 1, 1  }

/* Return number of consecutive hard regs needed starting at reg REGNO
   to hold something of mode MODE.
   This is ordinarily the length in words of a value of mode MODE
   but can be less for certain modes in special long registers.

   On the Alliant, ordinary registers hold 32 bits worth;
   for the FP registers, a single register is always enough for
   any floating-point value.  */
#define HARD_REGNO_NREGS(REGNO, MODE)   \
  ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE)	\
   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))

/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
   On the Alliant, the cpu registers can hold any mode but the FP registers
   can hold only floating point.  */
#define HARD_REGNO_MODE_OK(REGNO, MODE)		\
  ((REGNO) < 16 || GET_MODE_CLASS (MODE) == MODE_FLOAT	\
   || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)

/* Value is 1 if it is a good idea to tie two pseudo registers
   when one has mode MODE1 and one has mode MODE2.
   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
   for any hard reg, then this must be 0 for correct output.  */
#define MODES_TIEABLE_P(MODE1, MODE2)			\
   (((MODE1) == SFmode || (MODE1) == DFmode		\
     || (MODE1) == SCmode || (MODE1) == DCmode)		\
       == ((MODE2) == SFmode || (MODE2) == DFmode	\
	   || (MODE2) == SCmode || (MODE2) == DCmode))

/* Specify the registers used for certain standard purposes.
   The values of these macros are register numbers.  */

/* m68000 pc isn't overloaded on a register.  */
/* #define PC_REGNUM  */

/* Register to use for pushing function arguments.  */
#define STACK_POINTER_REGNUM 15

/* Base register for access to local variables of the function.  */
#define FRAME_POINTER_REGNUM 14

/* Value should be nonzero if functions must have frame pointers.
   Zero means the frame pointer need not be set up (and parms
   may be accessed via the stack pointer) in functions that seem suitable.
   This is computed in `reload', in reload1.c.  */
/* Set for now on Alliant until we find a way to make this work with
   their calling sequence.  */
#define FRAME_POINTER_REQUIRED 1

/* Base register for access to arguments of the function.  */
#define ARG_POINTER_REGNUM  8 

/* Register in which static-chain is passed to a function.  */
#define STATIC_CHAIN_REGNUM 10

/* Register in which address to store a structure value
   is passed to a function.  */
#define STRUCT_VALUE_REGNUM 9

/* Define the classes of registers for register constraints in the
   machine description.  Also define ranges of constants.

   One of the classes must always be named ALL_REGS and include all hard regs.
   If there is more than one class, another class must be named NO_REGS
   and contain no registers.

   The name GENERAL_REGS must be the name of a class (or an alias for
   another name such as ALL_REGS).  This is the class of registers
   that is allowed by "g" or "r" in a register constraint.
   Also, registers outside this class are allocated only when
   instructions express preferences for them.

   The classes must be numbered in nondecreasing order; that is,
   a larger-numbered class must never be contained completely
   in a smaller-numbered class.

   For any two classes, it is very desirable that there be another
   class that represents their union.  */

/* The Alliant has three kinds of registers, so eight classes would be
   a complete set.  One of them is not needed.  */

enum reg_class { NO_REGS, FP_REGS, DATA_REGS, DATA_OR_FP_REGS,
  ADDR_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES };

#define N_REG_CLASSES (int) LIM_REG_CLASSES

/* Give names of register classes as strings for dump file.   */

#define REG_CLASS_NAMES \
 { "NO_REGS", "FP_REGS", "DATA_REGS", "DATA_OR_FP_REGS",  \
   "ADDR_REGS", "GENERAL_REGS", "ALL_REGS" }

/* Define which registers fit in which classes.
   This is an initializer for a vector of HARD_REG_SET
   of length N_REG_CLASSES.  */

#define REG_CLASS_CONTENTS \
{					\
 0,		/* NO_REGS */		\
 0x00ff0000,	/* FP_REGS */		\
 0x000000ff,	/* DATA_REGS */		\
 0x00ff00ff,	/* DATA_OR_FP_REGS */	\
 0x0000ff00,	/* ADDR_REGS */		\
 0x0000ffff,	/* GENERAL_REGS */	\
 0x00ffffff	/* ALL_REGS */		\
}

/* The same information, inverted:
   Return the class number of the smallest class containing
   reg number REGNO.  This could be a conditional expression
   or could index an array.  */

extern enum reg_class regno_reg_class[];
#define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3])

/* The class value for index registers, and the one for base regs.  */

#define INDEX_REG_CLASS GENERAL_REGS
#define BASE_REG_CLASS ADDR_REGS

/* Get reg_class from a letter such as appears in the machine description.  */

#define REG_CLASS_FROM_LETTER(C) \
  ((C) == 'a' ? ADDR_REGS :			\
   ((C) == 'd' ? DATA_REGS :			\
    ((C) == 'f' ? FP_REGS :			\
     NO_REGS)))

/* The letters I, J, K, L and M in a register constraint string
   can be used to stand for particular ranges of immediate operands.
   This macro defines what the ranges are.
   C is the letter, and VALUE is a constant value.
   Return 1 if VALUE is in the range specified by C.

   For the 68000, `I' is used for the range 1 to 8
   allowed as immediate shift counts and in addq.
   `J' is used for the range of signed numbers that fit in 16 bits.
   `K' is for numbers that moveq can't handle.