gmicro.h

gcc-2.95.3 Linux下最常用的C编译器

/* Definitions of target machine for GNU compiler.  Gmicro (TRON) version.
   Copyright (C) 1987, 88, 89, 95, 96, 1997 Free Software Foundation, Inc.
   Contributed by Masanobu Yuhara, Fujitsu Laboratories LTD.
   ([e-mail])

This file is part of GNU CC.

GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING.  If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA.   */


/* Note that some other tm.h files include this one and then override
   many of the definitions that relate to assembler syntax.  */


/* Names to predefine in the preprocessor for this target machine.  */

#define CPP_PREDEFINES "-Dgmicro -Acpu(tron) -Amachine(tron)"

/* #define CPP_SPEC    ** currently not defined **/

/* #define CC1_SPEC    ** currently not defined **/


/* Print subsidiary information on the compiler version in use.  */
/*
#define TARGET_VERSION fprintf (stderr, " (Gmicro syntax)");
*/

/* Run-time compilation parameters selecting different hardware subsets.  */

extern int target_flags;

/* Macros used in the machine description to test the flags.  */

/* Compile for a Gmicro/300.  */
#define TARGET_G300 (target_flags & 1)
/* Compile for a Gmicro/200. */
#define TARGET_G200 (target_flags & 2)
/* Compile for a Gmicro/100. */
#define TARGET_G100 (target_flags & 4)

/* Compile FPU insns for floating point (not library calls).  */
#define TARGET_FPU (target_flags & 8)

/* Pop up arguments by called function. */
#define TARGET_RTD (target_flags & 0x10)

/* Compile passing first args in regs 0 and 1.
   This exists only to test compiler features that will be needed for
   RISC chips. It is not usable and is not intended to be usable on
   this cpu ;-< */
#define TARGET_REGPARM (target_flags & 0x20)

#define TARGET_BITFIELD (target_flags & 0x40)

#define TARGET_NEWRETURN (target_flags & 0x80)

/* Do not expand __builtin_smov (strcpy) to multiple movs.
   Use the smov instruction. */
#define TARGET_FORCE_SMOV (target_flags & 0x100)

/* default options are -m300, -mFPU,
   with bitfield instructions added because it won't always work otherwise.
   If there are versions of the gmicro that don't support bitfield instructions
   then it will take some thinking to figure out how to make them work.  */
#define TARGET_DEFAULT 0x49

/* Macro to define tables used to set the flags.
   This is a list in braces of pairs in braces,
   each pair being { "NAME", VALUE }
   where VALUE is the bits to set or minus the bits to clear.
   An empty string NAME is used to identify the default VALUE.  */

#define TARGET_SWITCHES  \
  { { "g300", 1},				\
    { "g200", 2},				\
    { "g100", 4},				\
    { "fpu", 8},				\
    { "soft-float", -8},			\
    { "rtd", 0x10},				\
    { "no-rtd", -0x10},				\
    { "regparm", 0x20},				\
    { "no-regparm", -0x20},			\
#if 0 /* Since we don't define PCC_BITFIELD_TYPE_MATTERS or use a large
	 STRUCTURE_SIZE_BOUNDARY, we must have bitfield instructions.  */
    { "bitfield", 0x40},			\
    { "no-bitfield", -0x40},			\
#endif
    { "newreturn", 0x80},			\
    { "no-newreturn", -0x80},			\
    { "force-smov", 0x100},			\
    { "no-force-smov", -0x100},			\
    { "", TARGET_DEFAULT}}


/* Blow away G100 flag silently off TARGET_fpu (since we can't clear
   any bits in TARGET_SWITCHES above) */
#define OVERRIDE_OPTIONS		\
{					\
  if (TARGET_G100) target_flags &= ~8;	\
}

/* target machine storage layout */

/* Define this if most significant bit is lowest numbered
   in instructions that operate on numbered bit-fields.
   This is true for Gmicro insns.
   We make it true always by avoiding using the single-bit insns
   except in special cases with constant bit numbers.  */
#define BITS_BIG_ENDIAN 1

/* Define this if most significant byte of a word is the lowest numbered.  */
/* That is true on the Gmicro.  */
#define BYTES_BIG_ENDIAN 1

/* Define this if most significant word of a multiword number is the lowest
   numbered.  */
/* For Gmicro we can decide arbitrarily
   since there are no machine instructions for them.  ????? */
#define WORDS_BIG_ENDIAN 0

/* number of bits in an addressable storage unit */
#define BITS_PER_UNIT 8

/* Width in bits of a "word", which is the contents of a machine register. */
#define BITS_PER_WORD 32

/* Width of a word, in units (bytes).  */
#define UNITS_PER_WORD 4

/* Width in bits of a pointer.
   See also the macro `Pmode' defined below.  */
#define POINTER_SIZE 32

/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
#define PARM_BOUNDARY 32

/* Boundary (in *bits*) on which stack pointer should be aligned.  */
#define STACK_BOUNDARY 32

/* Allocation boundary (in *bits*) for the code of a function.  */
/* Instructions of the Gmicro should be on half-word boundary */
/* But word boundary gets better performance */
#define FUNCTION_BOUNDARY 32

/* Alignment of field after `int : 0' in a structure.  */
#define EMPTY_FIELD_BOUNDARY 32

/* No data type wants to be aligned rounder than this. */
/* This is not necessarily 32 on the Gmicro */
#define BIGGEST_ALIGNMENT 32

/* Set this non-zero if move instructions will actually fail to work
   when given unaligned data.
   Unaligned data is allowed on Gmicro, though the access is slow. */

#define STRICT_ALIGNMENT 1
#define SLOW_UNALIGNED_ACCESS 1

/* Make strings word-aligned so strcpy from constants will be faster.  */
#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
  (TREE_CODE (EXP) == STRING_CST	\
   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))

/* Make arrays of chars word-aligned for the same reasons.  */
#define DATA_ALIGNMENT(TYPE, ALIGN)		\
  (TREE_CODE (TYPE) == ARRAY_TYPE		\
   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))

/* Define number of bits in most basic integer type.
   (If undefined, default is BITS_PER_WORD).  */
#define INT_TYPE_SIZE 32

/* #define PCC_BITFIELD_TYPE_MATTERS 1 ????? */

/* #define CHECK_FLOAT_VALUE (MODE, VALUE) ????? */


/* Standard register usage.  */

/* Number of actual hardware registers.
   The hardware registers are assigned numbers for the compiler
   from 0 to just below FIRST_PSEUDO_REGISTER.
   All registers that the compiler knows about must be given numbers,
   even those that are not normally considered general registers.
   For the Gmicro, we give the general registers numbers 0-15,
   and the FPU floating point registers numbers 16-31.  */
#define FIRST_PSEUDO_REGISTER 32

/* 1 for registers that have pervasive standard uses
   and are not available for the register allocator.
   On the Gmicro, the stack pointer and the frame pointer are
   such registers.  */
/* frame pointer is not indicated as fixed, because fp may be used freely
   when a frame is not built. */
#define FIXED_REGISTERS  \
 {0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 0, 1, \
  /* FPU registers.  */   \
  0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 0, 0, }

/* 1 for registers not available across function calls.
   These must include the FIXED_REGISTERS and also any
   registers that can be used without being saved.
   The latter must include the registers where values are returned
   and the register where structure-value addresses are passed.
   Aside from that, you can include as many other registers as you like.  */
#define CALL_USED_REGISTERS \
 {1, 1, 1, 1, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 0, 1, \
  /* FPU registers.  */   \
  1, 1, 1, 1, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 0, 0, }


/* Make sure everything's fine if we *don't* have a given processor.
   This assumes that putting a register in fixed_regs will keep the
   compilers mitt's completely off it.  We don't bother to zero it out
   of register classes.  If TARGET_FPU is not set,
   the compiler won't touch since no instructions that use these
   registers will be valid.  */
/*  This Macro is not defined now.
    #define CONDITIONAL_REGISTER_USAGE */

/* The Gmicro has no overlapping register */
/* #define OVERLAPPING_REGNO_P(REGNO) */

/* #define INSN_CLOBBERS_REGNO_P(INSN,REGNO)  */

/* Return number of consecutive hard regs needed starting at reg REGNO
   to hold something of mode MODE.
   This is ordinarily the length in words of a value of mode MODE
   but can be less for certain modes in special long registers.

   On the Gmicro, ordinary registers hold 32 bits worth;
   for the Gmicro/FPU registers, a single register is always enough for
   anything that can be stored in them at all.  */
#define HARD_REGNO_NREGS(REGNO, MODE)   \
  ((REGNO) >= 16 ? 1				\
   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))

/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
   On the Gmicro, the cpu registers can hold any mode but the FPU registers
   can hold only SFmode or DFmode.  And the FPU registers can't hold anything
   if FPU use is disabled. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
  ((REGNO) < 16								\
   || ((REGNO) < 32							\
       ? TARGET_FPU && (GET_MODE_CLASS (MODE) == MODE_FLOAT ||		\
			GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)	\
       : 0 ))

/* Value is 1 if it is a good idea to tie two pseudo registers
   when one has mode MODE1 and one has mode MODE2.
   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
   for any hard reg, then this must be 0 for correct output.  */
#define MODES_TIEABLE_P(MODE1, MODE2)			\
  (! TARGET_FPU						\
   || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT ||		\
	GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)	\
       == ((MODE2) == SFmode || (MODE2) == DFmode)))

/* Specify the registers used for certain standard purposes.
   The values of these macros are register numbers.  */

/* Gmicro pc isn't overloaded on a register.  */
/* #define PC_REGNUM  */

/* Register to use for pushing function arguments.  */
#define STACK_POINTER_REGNUM 15

/* Base register for access to local variables of the function.  */
#define FRAME_POINTER_REGNUM 14

/* Value should be nonzero if functions must have frame pointers.
   Zero means the frame pointer need not be set up (and parms
   may be accessed via the stack pointer) in functions that seem suitable.
   This is computed in `reload', in reload1.c.  */
#define FRAME_POINTER_REQUIRED 0

/* Base register for access to arguments of the function.  */
/* The Gmicro does not have hardware ap. Fp is treated as ap */
#define ARG_POINTER_REGNUM 14

/* Register in which static-chain is passed to a function.  */
#define STATIC_CHAIN_REGNUM 0

/* Register in which address to store a structure value
   is passed to a function.  */
#define STRUCT_VALUE_REGNUM 1

/* Define the classes of registers for register constraints in the
   machine description.  Also define ranges of constants.

   One of the classes must always be named ALL_REGS and include all hard regs.
   If there is more than one class, another class must be named NO_REGS
   and contain no registers.

   The name GENERAL_REGS must be the name of a class (or an alias for
   another name such as ALL_REGS).  This is the class of registers
   that is allowed by "g" or "r" in a register constraint.
   Also, registers outside this class are allocated only when
   instructions express preferences for them.

   The classes must be numbered in nondecreasing order; that is,
   a larger-numbered class must never be contained completely
   in a smaller-numbered class.

   For any two classes, it is very desirable that there be another
   class that represents their union.  */

/* The Gmicro has two kinds of registers, so four classes would be
   a complete set.  */

enum reg_class { NO_REGS, FPU_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES };

#define N_REG_CLASSES (int) LIM_REG_CLASSES

/* Give names of register classes as strings for dump file.   */

#define REG_CLASS_NAMES \
   { "NO_REGS", "FPU_REGS", "GENERAL_REGS", "ALL_REGS" }

/* Define which registers fit in which classes.
   This is an initializer for a vector of HARD_REG_SET
   of length N_REG_CLASSES.  */

#define REG_CLASS_CONTENTS \
{						\
     0,			/* NO_REGS */		\
     0xffff0000,	/* FPU_REGS */		\
     0x0000ffff,	/* GENERAL_REGS */	\
     0xffffffff		/* ALL_REGS */		\
}

/* The same information, inverted:
   Return the class number of the smallest class containing
   reg number REGNO.  This could be a conditional expression
   or could index an array.  */

extern enum reg_class regno_reg_class[];
#define REGNO_REG_CLASS(REGNO) ( (REGNO < 16) ? GENERAL_REGS : FPU_REGS )

/* The class value for index registers, and the one for base regs.  */

#define INDEX_REG_CLASS GENERAL_REGS
#define BASE_REG_CLASS  GENERAL_REGS
  
/* Get reg_class from a letter such as appears in the machine description.
   We do a trick here to modify the effective constraints on the
   machine description; we zorch the constraint letters that aren't
   appropriate for a specific target.  This allows us to guarantee
   that a specific kind of register will not be used for a given target
   without fiddling with the register classes above. */

#define REG_CLASS_FROM_LETTER(C) \
  ((C) == 'r' ? GENERAL_REGS :			\
   ((C) == 'f' ? (TARGET_FPU ? FPU_REGS : NO_REGS) :	\
     NO_REGS))

/* The letters I, J, K, L and M in a register constraint string
   can be used to stand for particular ranges of immediate operands.
   This macro defines what the ranges are.
   C is the letter, and VALUE is a constant value.
   Return 1 if VALUE is in the range specified by C.

   For the Gmicro, all immediate value optimizations are done 
   by assembler, so no machine dependent definition is necessary ??? */

/* #define CONST_OK_FOR_LETTER_P(VALUE, C) ((C) == 'I') */
#define CONST_OK_FOR_LETTER_P(VALUE, C) 0

/*
 * The letters G defines all of the floating constants tha are *NOT*
 * Gmicro-FPU constant.
 */

#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)	\
    ((C) == 'F' ||				\
     (C) == 'G' && !(TARGET_FPU && standard_fpu_constant_p (VALUE)))

/* Given an rtx X being reloaded into a reg required to be
   in class CLASS, return the class of reg to actually use.